• 技术刊物 Simulation Standard

Simulation Standard

Silvaco面向半导体工艺和器件仿真工程师推出的技术刊物

Touch Panel Capacitance Extraction in Hipex Full Chip Extraction Tool Using Stellar Field Solver

The previously standalone Stellar GUI based field solver tool for parasitic extraction is now integrated into Hipex (Silvaco’s full chip extraction tool) in Expert GUI. In Hipex, user can choose proper extraction method (including Steller solver) among different approaches. The GUI of Expert (Silvaco’s layout editor) has been extended to provide technology setup for Stellar mode of Hipex. Also, Expert provides full functional features of GDS drawing, editing and rule checking. As opposed to the Clever field solver based on adaptive meshing, Stellar can handle very large layout size with less memory and reduced runtime with acceptable accuracy (as compared to Clever). Clever, as very accurate adaptive meshing field solver, can be used as reference accuracy check when Stellar or rule based parasitic extraction method is performed in Hipex. In this article, we will review the basic interface of Hipex in Expert GUI using Stellar as a field solver to extract capacitance in touch panel example.

Dynamic Analysis of Liquid Crystal Pixels

We have demonstrated in previous articles the static electrical and optical simulation of LC cells [1][2]. The last piece of the function for a comprehensive analysis of an LC pixel is the capability of performing transient simulation. In this article, we will show the dynamic calculation of the LC director and the combination of electrical and optical simulation.

Hints, Tips and Solutions – Adding An Impurity to a Diffusion Model and Enable Diffusion of a New Impurity in a Specific Material

OBJECTIVEAdd an impurity (H) to a material (silicon) for a diffusion model (Fermi). The description below refers to Victory Process version 7.27.X.

3D Topography Simulation of SiC Epitaxial Growth Modeled by Diffusive Flux and Gibbs-Thomson Effect

One of wide bandgap semiconductors, SiC has been widely applied to the power devices, and then, the super-junction MOS transistor of SiC is being investigated to obtain higher performance for Ron and BV [1]. The super-junction structure is fabricated by trench filling with the epitaxial growth [2, 3].

An Empirical Composition Dependent Model of Dopant Diffusion Coefficients in Si, Si1-x Gex and Ge Material Systems

Previously published fast empirical models for diffusion coefficients in silicon-germanium (Si1-x Gex) [1][2] were not applicable to high germanium content x≥0.5 and hence did not properly extend towards germanium. For some dopants, diffusion coefficients become very small and hence this model cannot be applied to devices containing silicon-germanium with high germanium content or devices containing silicon, silicon-germanium and germanium

TCAD Simulation of Leakage Through Threading Dislocations in GaN-based pn-diodes

Gallium nitride (GaN)-based devices for power electronics show superior performance in comparison to silicon carbide and silicon-based devices [1]–[3]. The development of vertical devices, like pn-diodes and power HEMTs results in higher power density and voltage handling. One of the key parameters of this technology is the dislocation density. This is lower in free-standing GaN-on-GaN epitaxy than in heteroepitaxial GaN growth on different substrates like SiC or Si, but still has a density of 104-106 cm-2 [4]. The diode reverse leakage seems to be related to the dislocation density, and it can be modelled with a Poole-Frenkel or a hopping conduction mechanism [5]. The Poole-Frenkel model is already implemented in the trap-assisted tunnelling model in Silvaco Atlas [6]. For the leakage in threading dislocations a variable-range hopping (VRH) model has been implemented in the simulator, based on Ref. [7].