• Simulation Standard Technical Journal

Simulation Standard

Technical Journal

A Journal for Process and Device Engineers

Role of Netlist Extraction in Process Design Kits

Netlist extraction and the quality of netlist extraction is becoming of increasing concern for integrated circuit design flow. As circuits become more complicated with concomitant reductions in geometry, the design engineer faces the ever burgeoning demand of accurate of accurate netlist extraction. This simulation standard will detail this important area of netlist extraction and will provide an insight into Silvaco International’s netlist extraction tools to aid the circuit design engineer.

Parasitic Resistor Extraction with HIPEX-R

HIPEX-R is part of HIPEX software package for physical verification of multimillion transistor designs. It is a hierarchical full chip parasitic resistance extraction tool.

HIPEX-Net: New SILVACO Full-Chip LPE Tool vs. Maverick

SILVACO is releasing its new layout parameter extractor: HIPEX-NET. The new tool will replace Silvaco’s Maverick, which is a part of Guardian LVS/ERC. While being fully compliant with Maverick, HIPEX-NET has many advantages over Maverick. The comparison chart in Table 1 shows the critical features, which make HIPEX-NET much more powerful for layout verification than Maverick.

Measurement of Spacing Checks in Guardian DRC

In previous versions of Guardian DRC there were only two ways of measuring the distance between two segments: the ordinary, Euclidean metric, and the square metric, which behaves differently when measuring distances from a corner of a shape. With decreasing feature sizes Euclidean metric does not always provide the adequate measurement of tolerances required during the IC fabrication. Therefore various DRC systems introduced other types of measurement. This article describes how Guardian DRC system performs measurements required for the execution of DRC spacing checks, which are based on separations between line segments (“width”, “indistance”, “outdistance”, “ovdistance”, “distance”, “compdistance”).
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Highlighting Two Nodes in the Expert Layout Editor and Other Tips

Q: I would like to highlight two nodes at the same time in Expert. I currently use Verification->Node Probing->Pick Node to highlight a node, but I donít see how I can have 2 nets highlighted at the same time.

The Effect of Carrier Spilling on Spreading Resistance Profiling (SRP) Accuracy

Spreading Resistance Profiling (SRP) retains its popularity in the semiconductor industry by an inexpensive means of capturing dopant profile information. However, device engineers often incorporate SRP data into process simulation studies without properly considering SRP’s many limitations. Failing to account for these limitations jeopardizes the reliability of the data and potentially lead designers to incorrect conclusions about a device.