• Simulation Standard Technical Journal

Simulation Standard Technical Journal

A Journal for Process and Device Engineers

Gate Charging Simulation Using Atlas/MixedMode

IntroductionIn modern power devices, the total power loss comprises both a conductive power loss component and a capacitive loss component. As the cell pitch decreases, the conductive loss will decrease while the capacitive loss will increase. Therefore, for small cell pitch the capacitive power loss may be the dominant component of the total power loss in the device.

Using Athena Monte Carlo Module for Ion Implantation Simulation in Silicon Carbides

IntroductionThe Monte Carlo Implantation Module of ATHENA has proved to be a very accurate tool for simulation of various implantation processes. In this paper we demonstrate that the module can be successfully used not only for classical silicon-based technologies but also for other materials used in semiconductor industry. Silicon carbides were selected for this demonstration not only because they are widely used in power and high frequency electronics but also because they are most challenging objects for simulation due to their complicated lattice structures and electronic stopping models.

Is there a way to turn-off all of the generated layers

Is there a way to turn-off all of the generated layers so that the layout modifications can be done without them cluttering things?

Expert’s Netlist Driven Layout

Expert features a powerful Netlist Driven Layout (NDL) function to assist the user in creating a layout. It increases the productivity of layout design by automating cell generation and providing visual cues to assist in the wiring process. In this example, a latch circuit layout will be built based on developed child cells.

Expert Parametric Wires

Expert Parametric Wire (Pwire) is a complex group of objects containing, a single wire named master wire, any number of subparts such as enclosure wires, offset wires and sets of rectangles. Pwire objects enable extremely quick and efficient creation and editing of guard rings and shielded paths which are increasingly important due to higher integration density of IC designs.

I am currently using ATLAS/ Blaze to model the electrical properties of an LED device

I am currently using ATLAS/ Blaze to model the electrical properties of an LED device that I am investigating. Is it possible to examine the reverse ray trace from my simulated structure so that I can examine the angular distribution properties of the optical output of the device?