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Simulation Standard

Silvaco面向半导体工艺和器件仿真工程师推出的技术刊物

Hints & Tips December 1999

Q: I tried to resize shapes using the DRC command and observed thin "cracks" appeared for polygons with holes (see the left shape in Figure 1). At the same time Expert's "Resize selected" command does not create such cracks (see the right shape in Figure 1). I do not want DRC resizing command to produce "cracks". How can I achieve this?

An Intuitive Front-End to Effective and Efficient Schematic Capture Design

In our previous publication ("Scholar: An Enhanced Multi-Platform Schematic Capture", Simulation Standard, Vol.10, Number 9, September 1999) we presented the main features of a new-generation schematic capture tool - Silvaco's Scholar. In this article we are going to describe and analyze the graphical user interface (GUI) of Scholar.

Hints & Tips November 1999

A: ATLAS/S-Pisces and ATLAS/Blaze both have a small signal ac analysis capability built into them. This analysis is based upon the work of S.Laux [1] and results in the extraction of the Y parameter matrix. These Y parameters contain the conductance and capacitance information for each electrode in the device. This information allows the user to examine the frequency behavior of the CV simulation and also other parameters such as interface fixed charge, doping , oxide thickness, etc.

Modeling Bidirectional Thyristors Using ATLAS

Thyristors are semiconductor devices that exhibit multi-stable or bi-stable electrical characteristics, and can be switched between a high-impedance OFF state and a low-impedance ON state. Bidirectional thyristors are particularly useful for ac applications because they operate in the first and third quadrants of the I-V curve, depending on the anode and cathode polarities. It is useful to simulate and predict the important electrical characteristics of these devices, so they can be optimized for figures-of-merit such as breakover voltage, holding current, and switching speed.

Modelling Tunneling Currents in Ultra Thin Oxides

Ever decreasing minimum geometries in MOSFET design results in a corresponding reduction in the thickness of the gate oxide. This is an inevitable result of the increasing doping levels in the channel that are required to prevent depletion from the drain becoming too high a percentage of the total device length. For these new aggressive technologies, the required ultra thin gate oxides suffer a significant oxide tunnelling component. It has therefore become important to include this component in device modelling.

Optoelectric Device Simulation of a Dual-Base BJT Using Luminous

With the continuing emergence of optical technologies, optoelectronic device structures are becoming increasingly important for modern telecommunications and data network applications. Like other semiconductor technologies, two-dimensional numerical simulation can be an invaluable tool for studying and understanding semiconductor device behavior in response to optical stimulation. This article seeks to demonstrate the simulation of optoelectric device structures using Luminous.