• 技术刊物 Simulation Standard

Simulation Standard

Silvaco面向半导体工艺和器件仿真工程师推出的技术刊物

Fast and Accurate Simulation of the Steady-State of Voltage Controlled Oscillators with SmartSpice-RF

A novel simulation method of the steady-state of oscillators, based on Harmonic Balance (HB), is presented. A comparison with regular transient simulations demonstrates its advantages on a feedback voltage-controlled oscillator (VCO).

A Sophisticated Verilog-A Debugger

During the elaboration of a Verilog-A model, debugging a module can be very useful for detecting non-physical behavior or fine-tuning the model. The SILVACO Verilog-A debugger has been designed to meet these needs. It is available since version 2.6.0.R of SmartSpice and works along with SILVACO C-Interpreter. It allows iteration-per-iteration Verilog-A modules debugging. The debugger is tracing all the Verilog-A instantiations of the design, either instances of the SmartSpice netlist or in other Verilog-A modules.

Noise Simulations

If the MOS model file has the parameters: noia, noib, noic, Af, Kf and nlev=0 will SmartSpice ignore the BSIM III noise parameters (noia, noib and noic)

EDIF Conversion Flow on Gateway

EDIF has been a vital part of the Electronic Design Automation (EDA) industry for many years and Gateway allows users to convert edif200 formatted files of other tools vendors into Gateway’s schematics and symbols.

Hipex-CRC Parasitic RC-Network Reducer

Design of large scale chips requires precise knowledge of interconnect delays. However, detailed analysis of interconnects may quickly become computationally too expensive due to the distributed nature of the networks, and the large number of internal nodes extracted.

SET Accurate Compact Model for SET-MOSFET Hybrid Circuit Simulation

Single-Electron Transistors (SETs) [1][2] are attractive candidates for post-CMOS VLSI ICs. Accurate models are also required in order to efficiently design SET circuits and hybrid circuits