Simulating Impurity Freeze-Out During Low Temperature Operation

Introduction

The low temperature operation of many device structures has been shown as an effective method for improving device performance without reducing device size. Performance improvements for MOS-based technologies include increased operating speed, enhanced latch-up immunity, and better subthreshold characteristics [1]. By modeling low temperature phenomena, numerical simulation of device operation at low temperatures provides an effective means for analyzing such performance improvements before investing manufacturing time or money. It is the purpose of this paper to discuss the modeling of the dopant freeze-out phenomenon in ATLAS and provide an application example of its use.

At low temperatures, the thermal energy within a semiconductor is not high enough to fully activate all of the donor and acceptor impurity atoms. As a result, the carrier concentrations will not equal the concentration of dopant atoms. Figure 1 shows simulated data of the equilibrium electron concentration as a function of temperature for n-type silicon doped at 10cm. Below 100 K there is not enough thermal energy within the silicon to fully ionize the impurity atoms. This region of operation is known as the freeze-out regime. At temperatures between 100 K and 550 K, sufficient thermal energy resides within the silicon to fully ionize the impurity atoms. This region of operation is known as the extrinsic regime. As the temperature increases beyond 550 K, the intrinsic carrier concentration approaches and then exceeds the impurity concentration and the silicon returns to intrinsic-type behavior [2].