{"id":37097,"date":"1998-03-02T19:18:24","date_gmt":"1998-03-02T19:18:24","guid":{"rendered":"https:\/\/silvaco.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/circuit-verification-via-hypergraph-realization\/"},"modified":"2021-10-13T10:58:45","modified_gmt":"2021-10-13T17:58:45","slug":"circuit-verification-via-hypergraph-realization","status":"publish","type":"post","link":"https:\/\/silvaco.com\/zh-hans\/simulation-standard-zh-hans\/circuit-verification-via-hypergraph-realization\/","title":{"rendered":"Circuit Verification via Hypergraph Realization"},"content":{"rendered":"
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Circuit Verification via Hypergraph Realization<\/h1>\n

One of the most challenging and time consuming tasks in VLSI design automation is Layout Versus Schematic (LVS). The problem is to test the consistency between the actual circuit, represented by the layout, and the nominal circuit upon which the design was based. From mathematical point of view the core problem is the Hypergraph Isomorphism Problem (HIP)<\/p>\n

Unfortunately, it is known as NP-hard, so (as for most of CAD problems) it is extremely important to investigate the frequently encountered particular cases. It is well-known fact that particular case of HIP – Graph Isomorphism Problem – becomes easy solvable when input graphs are planar or have bounded parameters. Following this association, the series of investigations were done for estimation of complexity of the HIP in case of planar hypergraphs. Despite of this problem was proven as NP-hard even for very restricted input parameters, some polynomial-time algorithms were invented for cases when most of hyperedges (they correspond to particular VLSI subcircuits) have the bounded capacity. Fortunately, the classifi ed polynomially-solvable for planarity test hypergraphs are in the same time (being planar) easy checkable on isomorphism. This provides the real breakthrough in effi ciency of LVS tools used in Celebrity (Silvaco suite for VLSI Design Automation) for wide class of integrated circuits.<\/p>\n<\/div><\/section><\/div>

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