{"id":36965,"date":"1999-08-01T18:01:57","date_gmt":"1999-08-01T18:01:57","guid":{"rendered":"https:\/\/silvaco.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/generating-a-capacitance-coefficient-database-for-any-chip-level-lpe-tool-using-exact\/"},"modified":"2021-10-13T10:53:29","modified_gmt":"2021-10-13T17:53:29","slug":"generating-a-capacitance-coefficient-database-for-any-chip-level-lpe-tool-using-exact","status":"publish","type":"post","link":"https:\/\/silvaco.com\/zh-hans\/simulation-standard-zh-hans\/generating-a-capacitance-coefficient-database-for-any-chip-level-lpe-tool-using-exact\/","title":{"rendered":"Generating a Capacitance Coefficient Database for any Chip Level LPE Tool Using EXACT"},"content":{"rendered":"
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Generating a Capacitance Coefficient Database for any Chip Level LPE Tool Using\u00a0EXACT<\/i><\/h1>\n

1.0 Introduction<\/p>\n

EXACT<\/i><\/b>\u00a0is a sophisticated interconnect characterization tool integrated into the\u00a0DISCOVERY<\/i><\/b>\u00a0framework. It is designed to build the capacitance coefficient database required by any Layout Parasitic Extraction (LPE) tool. To calculate these coefficients accurately, an internal 3D process simulator creates test structures, such as shown in Figure 1.<\/p>\n

Then an integrated 3D field solver calculates the capacitance for each device layer and test structure combination. A simple internal script language then reformats the capacitance database so that it can be used with any chip level LPE tool.<\/p>\n<\/div><\/section><\/div>

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