{"id":36944,"date":"1999-11-03T18:39:55","date_gmt":"1999-11-03T18:39:55","guid":{"rendered":"https:\/\/silvaco.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/modelling-tunneling-currents-in-ultra-thin-oxides\/"},"modified":"2021-10-13T10:53:11","modified_gmt":"2021-10-13T17:53:11","slug":"modelling-tunneling-currents-in-ultra-thin-oxides","status":"publish","type":"post","link":"https:\/\/silvaco.com\/zh-hans\/simulation-standard-zh-hans\/modelling-tunneling-currents-in-ultra-thin-oxides\/","title":{"rendered":"Modelling Tunneling Currents in Ultra Thin Oxides"},"content":{"rendered":"
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Modelling Tunneling Currents in Ultra Thin Oxides<\/h1>\n

1. Introduction<\/p>\n

Ever decreasing minimum geometries in MOSFET design results in a corresponding reduction in the thickness of the gate oxide. This is an inevitable result of the increasing doping levels in the channel that are required to prevent depletion from the drain becoming too high a percentage of the total device length. For these new aggressive technologies, the required ultra thin gate oxides suffer a significant oxide tunnelling component. It has therefore become important to include this component in device modelling.<\/p>\n

For some time now, Silvaco has had models to deal with current conduction through oxides. It is only recently, however, that the number of questions to the customer support groups related to gate tunnelling effects has been increasing. It is appropriate, therefore to re-address this issue at this time.<\/p>\n

There are two types of models in Silvaco’s device simulator,\u00a0ATLAS<\/i><\/b>, which address oxide current conduction.<\/p>\n<\/div><\/section><\/div>

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