{"id":36852,"date":"2000-11-01T22:24:22","date_gmt":"2000-11-01T22:24:22","guid":{"rendered":"https:\/\/silvaco.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/simulation-of-vertical-double-gate-soi-mosfets-using-device3d\/"},"modified":"2021-10-13T10:47:37","modified_gmt":"2021-10-13T17:47:37","slug":"simulation-of-vertical-double-gate-soi-mosfets-using-device3d","status":"publish","type":"post","link":"https:\/\/silvaco.com\/zh-hans\/simulation-standard-zh-hans\/simulation-of-vertical-double-gate-soi-mosfets-using-device3d\/","title":{"rendered":"Simulation of Vertical Double-Gate SOI MOSFETs Using Device3D"},"content":{"rendered":"<div id='template_overview'  class='avia-section main_color avia-section-small avia-no-border-styling  avia-bg-style-scroll  avia-builder-el-0  el_before_av_section  avia-builder-el-first   container_wrap fullsize' style='background-color: #ffffff;  margin-top:0px; margin-bottom:0px; '  ><div class='container' ><main  role=\"main\" itemprop=\"mainContentOfPage\"  class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-36852'><div class='entry-content-wrapper clearfix'>\n<div class='flex_column_table av-equal-height-column-flextable -flextable' style='margin-top:20px; margin-bottom:0px; '><div class=\"flex_column av_three_fourth  flex_column_table_cell av-equal-height-column av-align-top first  avia-builder-el-1  el_before_av_one_fourth  avia-builder-el-first  \" style='padding:0px 0px 0px 0px ; border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/BlogPosting\" itemprop=\"blogPost\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1>Simulation of Vertical Double-Gate SOI MOSFETs Using Device3D<\/h1>\n<h3>Introduction<\/h3>\n<p>This article will present the simulation methodology of a self-aligned double-gate MOSFET structure (FinFET) using SILVACO 3-D simulation suite. The double-gate MOSFET is one of the most attractive alternative to classical MOSFET structure for gate length down to 20nm. The main advantage of the FinFET is the ability to drastically reduce the short channel effect. In spite of his double-gate structure, the FinFET is closed to its root, the conventional MOSFET in layout and fabrication. 3-D numerical simulations of the FinFET are performed in this article, in order to validate the basic principles and to uncover several important aspects: evaluation of the length , width and quantum effects.<\/p>\n<\/div><\/section><\/div><div class='av-flex-placeholder'><\/div><div class=\"flex_column av_one_fourth  flex_column_table_cell av-equal-height-column av-align-top av-zero-column-padding   avia-builder-el-3  el_after_av_three_fourth  avia-builder-el-last  \" style='border-radius:0px; ' id=\"whitepaper\" ><p><div  class='avia-builder-widget-area clearfix  avia-builder-el-4  el_before_av_image  avia-builder-el-first '><div id=\"nav_menu-29\" class=\"widget clearfix widget_nav_menu\"><div class=\"menu-simulation-standard-side-menu-chinese-simplified-container\"><ul id=\"menu-simulation-standard-side-menu-chinese-simplified\" class=\"menu\"><li id=\"menu-item-35571\" class=\"menu-item menu-item-type-post_type menu-item-object-page menu-item-35571\"><a href=\"https:\/\/silvaco.com\/zh-hans\/technical-library\/simulation-standard\/\">Simulation Standard<\/a><\/li>\n<\/ul><\/div><\/div><\/div><br \/>\n<div  class='avia-image-container  av-styling-    avia-builder-el-5  el_after_av_sidebar  el_before_av_button  avia-align-center '  itemprop=\"image\" itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/ImageObject\"  ><div class='avia-image-container-inner'><div class='avia-image-overlay-wrap'><a href=\"\/dynamicweb\/jsp\/downloads\/DownloadDocStepsAction.do?req=download&amp;nm=simstd_nov_2000_a2.pdf\" class='avia_image' target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" width=\"1280\" height=\"1669\" class='wp-image-22291 avia-img-lazy-loading-not-22291 avia_image' src=\"https:\/\/silvaco.com\/wp-content\/uploads\/simulationstandard\/simstd_nov_2000_a2.jpg\" alt='' title='simstd_nov_2000_a2'  itemprop=\"thumbnailUrl\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/simulationstandard\/simstd_nov_2000_a2.jpg 1280w, https:\/\/silvaco.com\/wp-content\/uploads\/simulationstandard\/simstd_nov_2000_a2-230x300.jpg 230w, https:\/\/silvaco.com\/wp-content\/uploads\/simulationstandard\/simstd_nov_2000_a2-790x1030.jpg 790w, https:\/\/silvaco.com\/wp-content\/uploads\/simulationstandard\/simstd_nov_2000_a2-768x1001.jpg 768w, https:\/\/silvaco.com\/wp-content\/uploads\/simulationstandard\/simstd_nov_2000_a2-1178x1536.jpg 1178w, https:\/\/silvaco.com\/wp-content\/uploads\/simulationstandard\/simstd_nov_2000_a2-1150x1500.jpg 1150w, https:\/\/silvaco.com\/wp-content\/uploads\/simulationstandard\/simstd_nov_2000_a2-541x705.jpg 541w, https:\/\/silvaco.com\/wp-content\/uploads\/simulationstandard\/simstd_nov_2000_a2-28x37.jpg 28w, https:\/\/silvaco.com\/wp-content\/uploads\/simulationstandard\/simstd_nov_2000_a2-42x55.jpg 42w, https:\/\/silvaco.com\/wp-content\/uploads\/simulationstandard\/simstd_nov_2000_a2-37x48.jpg 37w\" sizes=\"(max-width: 1280px) 100vw, 1280px\" \/><\/a><\/div><\/div><\/div><br \/>\n<div  class='avia-button-wrap avia-button-center  avia-builder-el-6  el_after_av_image  avia-builder-el-last ' ><a href='\/dynamicweb\/jsp\/downloads\/DownloadDocStepsAction.do?req=download&amp;nm=simstd_nov_2000_a2.pdf' class='avia-button  avia-color-grey   avia-icon_select-yes-right-icon avia-size-small avia-position-center ' target=\"_blank\" rel=\"noopener noreferrer\"><span class='avia_iconbox_title' >Download Simulation Standard<\/span><span class='avia_button_icon avia_button_icon_right' aria-hidden='true' data-av_icon='\ue875' data-av_iconfont='entypo-fontello'><\/span><\/a><\/div><\/p><\/div><\/div><!--close column table wrapper. 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Autoclose: 1 -->\n<\/p>\n","protected":false},"excerpt":{"rendered":"<p>This article will present the simulation methodology of a self-aligned double-gate MOSFET structure (FinFET) using SILVACO 3-D simulation suite. The double-gate MOSFET is one of the most attractive alternative to classical MOSFET structure for gate length down to 20nm. The main advantage of the FinFET is the ability to drastically reduce the short channel effect. In spite of his double-gate structure, the FinFET is closed to its root, the conventional MOSFET in layout and fabrication. 3-D numerical simulations of the FinFET are performed in this article, in order to validate the basic principles and to uncover several important aspects: evaluation of the length , width and quantum effects.<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[7723],"tags":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v24.0 (Yoast SEO v24.0) - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Simulation of Vertical Double-Gate SOI MOSFETs Using Device3D - Silvaco<\/title>\n<meta name=\"description\" content=\"Simulation of Vertical Double-Gate SOI MOSFETs Using Device3D\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/silvaco.com\/zh-hans\/simulation-standard-zh-hans\/simulation-of-vertical-double-gate-soi-mosfets-using-device3d\/\" \/>\n<meta property=\"og:locale\" content=\"zh_CN\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Simulation of Vertical Double-Gate SOI MOSFETs Using Device3D\" \/>\n<meta property=\"og:description\" content=\"Simulation of Vertical Double-Gate SOI MOSFETs Using Device3D\" \/>\n<meta property=\"og:url\" content=\"https:\/\/silvaco.com\/zh-hans\/simulation-standard-zh-hans\/simulation-of-vertical-double-gate-soi-mosfets-using-device3d\/\" \/>\n<meta property=\"og:site_name\" content=\"Silvaco\" \/>\n<meta property=\"article:publisher\" content=\"https:\/\/www.facebook.com\/SilvacoSoftware\/\" \/>\n<meta property=\"article:published_time\" content=\"2000-11-01T22:24:22+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2021-10-13T17:47:37+00:00\" \/>\n<meta name=\"author\" content=\"Graham Bell\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:creator\" content=\"@SilvacoSoftware\" \/>\n<meta name=\"twitter:site\" content=\"@SilvacoSoftware\" \/>\n<meta name=\"twitter:label1\" content=\"\u4f5c\u8005\" \/>\n\t<meta name=\"twitter:data1\" content=\"Graham Bell\" \/>\n\t<meta name=\"twitter:label2\" content=\"\u9884\u8ba1\u9605\u8bfb\u65f6\u95f4\" \/>\n\t<meta name=\"twitter:data2\" content=\"5 \u5206\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"WebPage\",\"@id\":\"https:\/\/silvaco.com\/zh-hans\/simulation-standard-zh-hans\/simulation-of-vertical-double-gate-soi-mosfets-using-device3d\/\",\"url\":\"https:\/\/silvaco.com\/zh-hans\/simulation-standard-zh-hans\/simulation-of-vertical-double-gate-soi-mosfets-using-device3d\/\",\"name\":\"Simulation of Vertical Double-Gate SOI MOSFETs Using Device3D - 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