{"id":36663,"date":"2003-09-01T21:17:12","date_gmt":"2003-09-01T21:17:12","guid":{"rendered":"https:\/\/silvaco.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/hipex-net-new-silvaco-full-chip-lpe-tool-vs-maverick\/"},"modified":"2021-10-13T10:40:34","modified_gmt":"2021-10-13T17:40:34","slug":"hipex-net-new-silvaco-full-chip-lpe-tool-vs-maverick","status":"publish","type":"post","link":"https:\/\/silvaco.com\/zh-hans\/simulation-standard-zh-hans\/hipex-net-new-silvaco-full-chip-lpe-tool-vs-maverick\/","title":{"rendered":"HIPEX-Net: New SILVACO Full-Chip LPE Tool vs. Maverick"},"content":{"rendered":"
\n

HIPEX-Net: New SILVACO Full-Chip LPE Tool vs. Maverick<\/h1>\n

Introduction<\/h3>\n

SILVACO is releasing its new layout parameter extractor: HIPEX-NET. The new tool will replace Silvaco\u2019s Maverick, which is a part of Guardian LVS\/ERC. While being fully compliant with Maverick, HIPEX-NET has many advantages over Maverick. The comparison chart in Table 1 shows the critical features, which make HIPEX-NET much more powerful for layout verification than Maverick.<\/p>\n\n\n\n\n\n\n\n\n\n\n
Feature<\/strong><\/td>\n\n
HIPEX-NET<\/strong><\/div>\n<\/td>\n
\n
Maverick<\/strong><\/div>\n<\/td>\n<\/tr>\n
SPICE netlist extraction<\/td>\n\n
Hierarchical and flat<\/div>\n<\/td>\n
\n
Flat only<\/div>\n<\/td>\n<\/tr>\n
Parameter extraction of transistors (MOSFET, MESFET, JFET, BJT) and design diodes, resistors, and capacitors<\/td>\n\n
Yes<\/div>\n<\/td>\n
\n
Yes<\/div>\n<\/td>\n<\/tr>\n
Integration with SILVACO layout editor, Expert<\/td>\n\n
Yes<\/div>\n<\/td>\n
\n
Yes<\/div>\n<\/td>\n<\/tr>\n
Hierarchical extraction<\/td>\n\n
Yes<\/div>\n<\/td>\n
\n
No<\/div>\n<\/td>\n<\/tr>\n
Advanced processing of net names<\/td>\n\n
Yes<\/div>\n<\/td>\n
\n
No<\/div>\n<\/td>\n<\/tr>\n
Schematic backannotation<\/td>\n\n
Yes<\/div>\n<\/td>\n
\n
No<\/div>\n<\/td>\n<\/tr>\n
Compatibility with HIPEX parasitic tools<\/td>\n\n
Yes<\/div>\n<\/td>\n
\n
No<\/div>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Table 1.\u00a0HIPEX-NET<\/em><\/strong>\u00a0vs.\u00a0Maverick<\/em><\/strong>: features comparison chart<\/p>\n

HIPEX-NET\u00a0<\/strong><\/em>is a full-chip hierarchical netlist extractor. It can handle very complex layout hierarchy, this is in stark contrast to\u00a0Maverick<\/em><\/strong>\u00a0, where\u00a0Maverick<\/em><\/strong>\u00a0must flatten the layout. As a result,HIPEX-NET<\/em><\/strong>\u00a0works much faster and needs less memory to process big hierarchical layouts. Today\u00a0HIPEX-NET<\/em><\/strong>\u00a0successfully extracts 10 million transistor layouts on Win32 platform, which provides only 2GB of virtual memory. The 64-bit version available for SunOS can handle much larger layouts.<\/p>\n<\/div><\/section><\/div>

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