{"id":36643,"date":"2003-11-04T20:05:07","date_gmt":"2003-11-04T20:05:07","guid":{"rendered":"https:\/\/silvaco.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/interconnect-parasitic-accuracy-speed-improvements-in-new-clever-release\/"},"modified":"2021-10-13T10:40:16","modified_gmt":"2021-10-13T17:40:16","slug":"interconnect-parasitic-accuracy-speed-improvements-in-new-clever-release","status":"publish","type":"post","link":"https:\/\/silvaco.com\/zh-hans\/simulation-standard-zh-hans\/interconnect-parasitic-accuracy-speed-improvements-in-new-clever-release\/","title":{"rendered":"Interconnect Parasitic Accuracy & Speed Improvements in New CLEVER Release"},"content":{"rendered":"
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Interconnect Parasitic Accuracy & Speed Improvements in New Clever Release<\/h1>\n

Introduction<\/strong><\/p>\n

This article introduces the new features and numerical schema implemented in the most recent release of Clever <\/i><\/b>from Silvaco. In this new release, both memory handling and simulation time are optimized to allow the input of larger simulation structures. In addition, the release offers greater control over the accuracy benchmarks necessary for extracted parasitic elements.<\/p>\n

Parasitic Extraction Accuracy<\/strong><\/p>\n

Accurate parasitic extraction is crucial for deep submicron designs. Today, 3D field solvers are touted as the benchmark of accuracy, but any field solver is only as accurate as its input geometry. Clever <\/i><\/b>achieves greater accuracy by using a combination of 3D process simulation and 3D field solver capabilities. All back end processes, including deposition, etching, and lithography, are performed before generation of the final structure geometry. This makes it possible to obtain an accurate 3D topology of the layout, while offering greater power and flexibility in extracting highly accurate parasitic resistances and capacitances in deep and ultra-deep submicron designs. (Figure 1)<\/p>\n<\/div><\/section><\/div>

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