{"id":36605,"date":"2004-03-01T00:55:17","date_gmt":"2004-03-01T00:55:17","guid":{"rendered":"https:\/\/silvaco.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/hierarchical-layout-versus-schematic\/"},"modified":"2021-10-13T10:39:27","modified_gmt":"2021-10-13T17:39:27","slug":"hierarchical-layout-versus-schematic","status":"publish","type":"post","link":"https:\/\/silvaco.com\/zh-hans\/simulation-standard-zh-hans\/hierarchical-layout-versus-schematic\/","title":{"rendered":"Hierarchical Layout versus Schematic"},"content":{"rendered":"
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Hierarchical Layout versus Schematic<\/h1>\n

1. Introduction<\/strong><\/p>\n

A new Hierarchical Layout versus Schematic (HLVS) system that provides significant improvement in verification of huge circuits is described. Other of LVS verification tools perform a netlist flattening and comparison in transistor level [1, 2]. These tools are based on standard graph isomorphism algorithms and are sufficiently efficient in practice. Their running time is almost linear in the size of compared devices: O (Nm<\/sub>), where N is the number of compared devices and m is value a little larger than 1. These tools are not effective enough to verify circuits containing tens of millions of transistors. There is a need for hierarchical comparison of two netlists. This proposed hierarchical approach does not flatten the netlist. The comparison is carried out for separate cells. Once a cell is checked, its contents are not used later in comparison, only the verification of connectivity to ports of this cell is performed. This approach enables a large decrease in the number of compared elements and, consequently, the run time of HLVS verification.<\/p>\n

2. Some Features of Guardian HLVS<\/strong><\/p>\n

Compared netlists should satisfy to some conditions to make hierarchical verification more effective:<\/p>\n