{"id":36557,"date":"2004-10-01T00:04:17","date_gmt":"2004-10-01T00:04:17","guid":{"rendered":"https:\/\/silvaco.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/a-sophisticated-verilog-a-debugger\/"},"modified":"2021-10-13T10:36:13","modified_gmt":"2021-10-13T17:36:13","slug":"a-sophisticated-verilog-a-debugger","status":"publish","type":"post","link":"https:\/\/silvaco.com\/zh-hans\/simulation-standard-zh-hans\/a-sophisticated-verilog-a-debugger\/","title":{"rendered":"A Sophisticated Verilog-A Debugger"},"content":{"rendered":"<div id='template_overview'  class='avia-section main_color avia-section-small avia-no-border-styling  avia-bg-style-scroll  avia-builder-el-0  el_before_av_section  avia-builder-el-first   container_wrap fullsize' style='background-color: #ffffff;  margin-top:0px; margin-bottom:0px; '  ><div class='container' ><main  role=\"main\" itemprop=\"mainContentOfPage\"  class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-36557'><div class='entry-content-wrapper clearfix'>\n<div class='flex_column_table av-equal-height-column-flextable -flextable' style='margin-top:20px; margin-bottom:0px; '><div class=\"flex_column av_three_fourth  flex_column_table_cell av-equal-height-column av-align-top first  avia-builder-el-1  el_before_av_one_fourth  avia-builder-el-first  \" style='padding:0px 0px 0px 0px ; border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/BlogPosting\" itemprop=\"blogPost\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1>A Sophisticated Verilog-A Debugger<\/h1>\n<p>During the elaboration of a\u00a0<strong><em>Verilog-A<\/em><\/strong>\u00a0model, debugging a module can be very useful for detecting non-physical behavior or fine-tuning the model. The SILVACO\u00a0<strong><em>Verilog-A<\/em><\/strong>\u00a0debugger has been designed to meet these needs. It is available since version 2.6.0.R of\u00a0<strong><em>SmartSpice<\/em><\/strong>\u00a0and works along with SILVACO C-Interpreter. It allows iteration-per-iteration\u00a0<strong><em>Verilog-A<\/em><\/strong>\u00a0modules debugging. The debugger is tracing all the\u00a0<strong><em>Verilog-A<\/em><\/strong>\u00a0instantiations of the design, either instances of the\u00a0<strong><em>SmartSpice<\/em><\/strong>\u00a0netlist or in other\u00a0<strong><em>Verilog-A<\/em><\/strong>\u00a0modules.<\/p>\n<p>The BSIM4\u00a0<strong><em>Verilog-A<\/em><\/strong>\u00a0model (bsim4.va) and the adder design (adder.in) used as an example are freely available on SILVACO website.<\/p>\n<p>It can be enabled by setting in the input deck:<\/p>\n<blockquote>\n<p><span style=\"font-family: Courier New, Courier, mono;\">.OPTIONS va_mode=debug<\/span><\/p>\n<\/blockquote>\n<p>The debugger appears when the simulation of this input deck is launched. The simulation stops at the first instruction (a breakpoint at the first instruction is always set by default). In the case of BSIM4 model, the first instruction encountered is the initial_step event in the analog block. The layout of the main window at startup<\/p>\n<p>The\u00a0<strong><em>Verilog-A<\/em><\/strong>\u00a0source code is displayed in an editor window. Syntax highlighting is available and its colors are fully customizable. Line numbers can be displayed by checking the \u201cShow line number\u201d box in the Properties dialog window (Edit &gt; Properties&#8230;).<\/p>\n<p>The console window is at the bottom of the main window. The error messages are printed in this area and the user can enter commands manually.<\/p>\n<p>In this example (Figure 2. The console window), a breakpoint has been set at line 2699 (the end of the initial_step block) and the simulation has been started with the cont command. The edit window has now the aspect.<\/p>\n<\/div><\/section><\/div><div class='av-flex-placeholder'><\/div><div class=\"flex_column av_one_fourth  flex_column_table_cell av-equal-height-column av-align-top av-zero-column-padding   avia-builder-el-3  el_after_av_three_fourth  avia-builder-el-last  \" style='border-radius:0px; ' id=\"whitepaper\" ><p><div  class='avia-builder-widget-area clearfix  avia-builder-el-4  el_before_av_image  avia-builder-el-first '><div id=\"nav_menu-29\" class=\"widget clearfix widget_nav_menu\"><div class=\"menu-simulation-standard-side-menu-chinese-simplified-container\"><ul id=\"menu-simulation-standard-side-menu-chinese-simplified\" class=\"menu\"><li id=\"menu-item-35571\" class=\"menu-item menu-item-type-post_type menu-item-object-page menu-item-35571\"><a href=\"https:\/\/silvaco.com\/zh-hans\/technical-library\/simulation-standard\/\">Simulation Standard<\/a><\/li>\n<\/ul><\/div><\/div><\/div><br \/>\n<div  class='avia-image-container  av-styling-    avia-builder-el-5  el_after_av_sidebar  el_before_av_button  avia-align-center '  itemprop=\"image\" itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/ImageObject\"  ><div class='avia-image-container-inner'><div class='avia-image-overlay-wrap'><a href=\"\/dynamicweb\/jsp\/downloads\/DownloadDocStepsAction.do?req=download&amp;nm=simstd_oct_2004_a3.pdf\" class='avia_image' target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" width=\"644\" height=\"800\" class='wp-image-22549 avia-img-lazy-loading-not-22549 avia_image' src=\"https:\/\/silvaco.com\/wp-content\/uploads\/simulationstandard\/simstd_oct_2004_a3-e1611193421702.jpg\" alt='' title='simstd_oct_2004_a3'  itemprop=\"thumbnailUrl\"  \/><\/a><\/div><\/div><\/div><br \/>\n<div  class='avia-button-wrap avia-button-center  avia-builder-el-6  el_after_av_image  avia-builder-el-last ' ><a href='\/dynamicweb\/jsp\/downloads\/DownloadDocStepsAction.do?req=download&amp;nm=simstd_oct_2004_a3.pdf' class='avia-button  avia-color-grey   avia-icon_select-yes-right-icon avia-size-small avia-position-center ' target=\"_blank\" rel=\"noopener noreferrer\"><span class='avia_iconbox_title' >Download Simulation Standard<\/span><span class='avia_button_icon avia_button_icon_right' aria-hidden='true' data-av_icon='\ue875' data-av_iconfont='entypo-fontello'><\/span><\/a><\/div><\/p><\/div><\/div><!--close column table wrapper. Autoclose: 1 --><\/div><\/div><\/main><!-- close content main element --><\/div><\/div><div id='av_section_2'  class='avia-section main_color avia-section-small avia-no-border-styling  avia-bg-style-scroll  avia-builder-el-7  el_after_av_section  avia-builder-el-last   container_wrap fullsize' style='background-color: #ffffff;  margin-top:0px; margin-bottom:0px; '  ><div class='container' ><div class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-36557'><div class='entry-content-wrapper clearfix'>\n<div class='flex_column_table av-equal-height-column-flextable -flextable' style='margin-top:20px; margin-bottom:0px; '><div class=\"flex_column av_one_full  flex_column_table_cell av-equal-height-column av-align-top first  avia-builder-el-8  avia-builder-el-no-sibling  \" style='padding:0px 0px 0px 0px ; border-radius:0px; '><\/div><\/div><!--close column table wrapper. Autoclose: 1 -->\n<\/p>\n","protected":false},"excerpt":{"rendered":"<p>During the elaboration of a\u00a0Verilog-A\u00a0model, debugging a module can be very useful for detecting non-physical behavior or fine-tuning the model. The SILVACO\u00a0Verilog-A\u00a0debugger has been designed to meet these needs. It is available since version 2.6.0.R of\u00a0SmartSpice\u00a0and works along with SILVACO C-Interpreter. It allows iteration-per-iteration\u00a0Verilog-A\u00a0modules debugging. The debugger is tracing all the\u00a0Verilog-A\u00a0instantiations of the design, either instances of the\u00a0SmartSpice\u00a0netlist or in other\u00a0Verilog-A\u00a0modules.<\/p>\n","protected":false},"author":3,"featured_media":22549,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[7723],"tags":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v24.0 (Yoast SEO v24.0) - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>A Sophisticated Verilog-A Debugger - Silvaco<\/title>\n<meta name=\"description\" content=\"During the elaboration of a\u00a0Verilog-A\u00a0model, debugging a module can be very useful for detecting non-physical behavior or fine-tuning the model.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/silvaco.com\/zh-hans\/simulation-standard-zh-hans\/a-sophisticated-verilog-a-debugger\/\" \/>\n<meta property=\"og:locale\" content=\"zh_CN\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"A Sophisticated Verilog-A Debugger\" \/>\n<meta property=\"og:description\" content=\"During the elaboration of a\u00a0Verilog-A\u00a0model, debugging a module can be very useful for detecting non-physical behavior or fine-tuning the model.\" \/>\n<meta property=\"og:url\" content=\"https:\/\/silvaco.com\/zh-hans\/simulation-standard-zh-hans\/a-sophisticated-verilog-a-debugger\/\" \/>\n<meta property=\"og:site_name\" content=\"Silvaco\" \/>\n<meta property=\"article:publisher\" content=\"https:\/\/www.facebook.com\/SilvacoSoftware\/\" \/>\n<meta property=\"article:published_time\" content=\"2004-10-01T00:04:17+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2021-10-13T17:36:13+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/silvaco.com\/wp-content\/uploads\/simulationstandard\/simstd_oct_2004_a3-e1611193421702.jpg\" \/>\n\t<meta property=\"og:image:width\" content=\"644\" \/>\n\t<meta property=\"og:image:height\" content=\"800\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/jpeg\" \/>\n<meta name=\"author\" content=\"Erick Castellon\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:creator\" content=\"@SilvacoSoftware\" \/>\n<meta name=\"twitter:site\" content=\"@SilvacoSoftware\" \/>\n<meta name=\"twitter:label1\" content=\"\u4f5c\u8005\" \/>\n\t<meta name=\"twitter:data1\" content=\"Erick Castellon\" \/>\n\t<meta name=\"twitter:label2\" content=\"\u9884\u8ba1\u9605\u8bfb\u65f6\u95f4\" \/>\n\t<meta name=\"twitter:data2\" content=\"5 \u5206\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"WebPage\",\"@id\":\"https:\/\/silvaco.com\/zh-hans\/simulation-standard-zh-hans\/a-sophisticated-verilog-a-debugger\/\",\"url\":\"https:\/\/silvaco.com\/zh-hans\/simulation-standard-zh-hans\/a-sophisticated-verilog-a-debugger\/\",\"name\":\"A Sophisticated Verilog-A Debugger - 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