{"id":36507,"date":"2005-08-01T00:02:07","date_gmt":"2005-08-01T00:02:07","guid":{"rendered":"https:\/\/silvaco.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/gate-charging-simulation-using-atlas-mixedmode\/"},"modified":"2021-10-13T10:35:20","modified_gmt":"2021-10-13T17:35:20","slug":"gate-charging-simulation-using-atlas-mixedmode","status":"publish","type":"post","link":"https:\/\/silvaco.com\/zh-hans\/simulation-standard-zh-hans\/gate-charging-simulation-using-atlas-mixedmode\/","title":{"rendered":"Gate Charging Simulation Using Atlas\/MixedMode"},"content":{"rendered":"
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Gate Charging Simulation Using ATLAS\/MixedMode<\/h1>\n

Introduction<\/h3>\n

In modern power devices, the total power loss comprises both a conductive power loss component and a capacitive loss component. As the cell pitch decreases, the conductive loss will decrease while the capacitive loss will increase. Therefore, for small cell pitch the capacitive power loss may be the dominant component of the total power loss in the device.<\/p>\n

There is clearly a need for a method that will allow analysis of the capacitive component of the power loss. One technique to do this in a power UMOSFET device is to analyze the gate charging time using\u00a0ATLAS\/MixedMode<\/em><\/strong>.<\/p>\n

ATLAS\/MixedMode<\/strong><\/em>\u00a0is a circuit simulator that can include elements simulated using device simulation, as well as compact circuit models.<\/p>\n

Device Structure and Circuit<\/h3>\n

As shown in Figure 1, this design has a U-Groove in the gate region, and has a higher channel density which reduces the on-resistance as compared to VMOSFETs or DMOSFETs.<\/p>\n

Effects of device size and transconductance makes power loss component analysis more difficult. A more useful parameter from the circuit design point of view is the gate charge rather than capacitance. Figure 2 shows the gate charge simulation test circuit.<\/p>\n<\/div><\/section><\/div>

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