{"id":36460,"date":"2007-02-01T00:01:28","date_gmt":"2007-02-01T00:01:28","guid":{"rendered":"https:\/\/silvaco.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/a-semi-analytical-model-for-the-subthreshold-behavior-of-finflash-structures\/"},"modified":"2021-10-13T10:31:00","modified_gmt":"2021-10-13T17:31:00","slug":"a-semi-analytical-model-for-the-subthreshold-behavior-of-finflash-structures","status":"publish","type":"post","link":"https:\/\/silvaco.com\/zh-hans\/simulation-standard-zh-hans\/a-semi-analytical-model-for-the-subthreshold-behavior-of-finflash-structures\/","title":{"rendered":"A Semi-Analytical Model for the Subthreshold Behavior of FinFLASH Structures"},"content":{"rendered":"
\n

A Semi-Analytical Model for the Subthreshold Behavior of FinFLASH Structures<\/h1>\n

L. Perniola, J. Razafindramora, P. Scheiblin, F. Daug\u00b4e, C. Jahan, B. De Salvo, G. Reimbold, F. Boulanger
\nCEA-LETI
\n17, Rue des Martyrs, F – 38054, Grenoble, France, luca.perniola@cea.fr
\nG. Ghibaudo
\nINP Grenoble MINATEC
\n3, Parvis Louis N\u00b4eel, BP 257, 38016 Grenoble Cedex 1<\/em><\/p>\n

Abstract<\/h3>\n

In this paper we present an original semi-analytical model for the subthreshold electrical behavior of complex 3D structures as the SOI FinFLASH devices. This physically-based model, which does not need any fitting parameter, solves the Poisson equation for a fin covered by trapped charges in the active dielectrics. The analytical results are compared with fully 3D numerical simulations and a good agreement is obtained down to fins with very small feature sizes (order of tens of nm). This model can be efficiently used to gain information on important cell electrical behaviors as the threshold voltage shift Vth and the subthreshold slope factor S.<\/p>\n

Introduction<\/h3>\n

The FinFLASH device in trigate (W \u2248 H, see Fig. 1) or double-gate (H _ W) configuration is currently investigated as one of the most promising solutions to replace conventional planar FLASH structures beyond the 32 nm technology node[1]-[2]. The main advantages of the FinFLASH device are its compact layout, moreover fully compatible with future generations of multi-gate CMOS, and its excellent electrical performance due to the enhanced coupling between the gate and the active channel. In this frame, it is today of utmost importance to provide a simple approach which allows us to describe the most important electrical parameters of the memory operation without applying time consuming 3D numerical simulations.<\/p>\n<\/div><\/section><\/div>

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