{"id":36119,"date":"2017-01-01T17:41:14","date_gmt":"2017-01-01T17:41:14","guid":{"rendered":"https:\/\/silvaco.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/thermo-mechanical-stress-in-through-silicon-vias\/"},"modified":"2021-10-13T09:51:58","modified_gmt":"2021-10-13T16:51:58","slug":"thermo-mechanical-stress-in-through-silicon-vias","status":"publish","type":"post","link":"https:\/\/silvaco.com\/zh-hans\/simulation-standard-zh-hans\/thermo-mechanical-stress-in-through-silicon-vias\/","title":{"rendered":"Thermo-mechanical Stress in Through-Silicon-Vias"},"content":{"rendered":"
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Thermo-mechanical Stress in Through-Silicon-Vias<\/h1>\n

1. Introduction<\/strong><\/p>\n

During the last several years, the enhancement of integrated circuits (ICs) performance and power consumption have contributed to the continual scaling down the size of transistors. However, scaling down semiconductor devices has brought serious challenges to the materials and processes of on-chip interconnects beyond the 32-nm technology node. Therefore, some researchers proposed another direction to increase the device density by making ICs into three-dimensional (3D) spaces and the 3D IC stacking has attracted tremendous attention for IC integration in order to reduce wire length and footprint.<\/p>\n

Through silicon via (TSV) is regarded as the best choice of the connection between wafer and wafer. By using TSVs in 3D integration, the system performance can be significantly improved and the manufacturing cost is reduced. However, there are still some challenges in this technology.<\/p>\n

The major reliability concern has to do with the high thermal expansion mismatch stresses caused by the dissimilar materials of the high expansion copper (Cu) and low expansion silicon (Si). These thermal stresses, which are ubiquitously induced during processing and thermal cycling of TSV structures, can potentially degrade the performance of stress-sensitive devices around the TSVs or drive crack growth in 3D interconnects. Therefore, the success of 3D integration largely relies on the thermo-mechanical stresses developed in the system and its impact on reliability.
\nFinite element methods have been widely used to numerically analyze the thermo-mechanical stresses in 3D structures and regarded as the only conceivable approach for analyzing and characterizing stress in circuits accompanied with complicated structures. Silvaco tools, especially Victory Process, can be used for 3D TSV stress simulation. In this article, an analytical approach based on classical Lame problem in elasticity was used to verify 3D FEM solutions from Victory Process.<\/p>\n<\/div><\/section><\/div>

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