TFT panels have already gained their undisputable reputation in a variety of professional and commercial applications. High quality, ease of customization, and comparably low manufacturing costs position these panels as an attractive solution offered by standard and custom color display industry. To accomplish the goals set by ever increasing quality standards, TFT panel circuits constantly expand their functionality, add new features. This process naturally leads to an increased complexity of the display systems and, as a consequence, is accompanied by a strong demand for higher operating speeds. Traditionally, implementation of the solutions satisfying these tough requirements in the industry is accompanied by device feature size reduction and by placing more and more elements of the system chips. Modern TFT panel circuits contain millions of active and passive devices and their chip sizes continue to grow with every new generation.<\/p>\n
Increased functionality, complexity, and higher speed cause more signal activity in the TFT panels during their operation. With the reduction in feature size devices start exhibiting new physical phenomena including the small-geometry effects, self-heating, leakage, tunneling, etc. These effects have to be properly reflected in the device models to produce accurate and reliable results during simulation of the systems at the design verification stage.<\/p>\n
In practice, verification of TFT panel chip functionality becomes a real challenge. Size of TFT panel circuits, complex and very non-uniform signal activity profile, performance requirements might lead to the situation where traditional simulation of these circuits (using SPICE) becomes computationally inefficient and near impractical. In this paper, we demonstrate that Fast-SPICE simulators, represented in this work by SmartSpicePro, offer an efficient solution to this problem.<\/p>\n
![\"\"](\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/03\/simstd_Q3_2017_a4-1.jpg\")
<\/p>\n