{"id":35940,"date":"2019-04-24T16:05:37","date_gmt":"2019-04-24T16:05:37","guid":{"rendered":"https:\/\/silvaco.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/unraveling-and-optimizing-transistor-level-simulation\/"},"modified":"2026-10-15T15:01:38","modified_gmt":"2026-10-15T22:01:38","slug":"unraveling-and-optimizing-transistor-level-simulation","status":"publish","type":"post","link":"https:\/\/silvaco.com\/zh-hans\/analog-custom-design-zh-hans\/spice-zh-hans\/spice-webinars-zh-hans\/unraveling-and-optimizing-transistor-level-simulation\/","title":{"rendered":"Unraveling and Optimizing Transistor-Level Simulation"},"content":{"rendered":"<p><img fetchpriority=\"high\" decoding=\"async\" class=\"cleaned-enfold-image\" src=\"https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar.jpg\" sizes=\"auto, (max-width: 1920px) 100vw, 1920px\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar.jpg 1920w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-300x31.jpg 300w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-1030x108.jpg 1030w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-768x80.jpg 768w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-1536x161.jpg 1536w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-1500x157.jpg 1500w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-705x74.jpg 705w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-43x5.jpg 43w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-63x7.jpg 63w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-48x5.jpg 48w\" alt=\"Banner Blue\" width=\"1920\" height=\"201\" \/><\/p>\n<p>Circuit Simulation is one of the most critical parts of the design process. Validating circuit behavior is essential to saving cost, minimize turn-around times and establishing reliable system characteristics before IC manufacture. To maximize throughput and efficiency, it is necessary to understand the internal methodologies and processes happening inside SPICE simulations. In this webinar, we will be presenting an in-depth understanding of the core of the SmartSpice simulator, including parallel and FastSPICE analysis modes.<\/p>\n<p>After the webinar, attendees will be able to optimize the performance of SmartSpice and SmartSpice Pro in accordance with their design applications and methodology to achieve the ideal balance of Accuracy-of-analysis versus Speed-of-analysis.<\/p>\n<h2>What attendees will learn:<\/h2>\n<ul id=\"web-bullet\">\n<li>Simulation Process and Framework\n<ul>\n<li>Convergence<\/li>\n<li>Numerical Integration<\/li>\n<li>Timestep Control<\/li>\n<\/ul>\n<\/li>\n<li>FastSPICE Simulation Technology<\/li>\n<li>Trading off Accuracy versus Speed<\/li>\n<\/ul>\n<h2>Presenter<\/h2>\n<p><img decoding=\"async\" class=\"alignleft wp-image-4710 size-thumbnail\" src=\"\/wp-content\/uploads\/2020\/02\/robert1-80x80.jpg\" alt=\"\" width=\"80\" height=\"80\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/robert1-80x80.jpg 80w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/robert1-36x36.jpg 36w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/robert1-180x180.jpg 180w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/robert1-37x37.jpg 37w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/robert1-55x55.jpg 55w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/robert1-48x48.jpg 48w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/robert1.jpg 273w\" sizes=\"(max-width: 80px) 100vw, 80px\" \/>Robert Villanueva is an Applications Engineer within the Front-End EDA Division working on numerous simulation technologies and responsible for Silvaco\u2019s FastSPICE Simulator worldwide support. He is active in the Si2-Compact Model Coalition and HiSIM Consortium &#8211; SPICE Model Standardization Groups. With more than 15 years in the IC design and EDA industry, he is well experienced in CMOS circuit designs, empirical models, and various major commercial circuit simulators.<\/p>\n<p>Mr. Villanueva holds a Bachelor and a Master\u2019s Degree in Electronics and Communications Engineering from Saint Louis University Philippines (Cum Laude). He is a duly licensed Electronics and Communications Engineer by the Philippine Professional Regulation Commission.<\/p>\n<p><strong>When<\/strong>: April 25, 2019<br \/>\n<strong>Where<\/strong>: Online<br \/>\n<strong>Time<\/strong>: 10:00am-11:00am &#8211; (PST)<br \/>\n<strong>Language<\/strong>: English<\/p>\n<h3>WHO SHOULD ATTEND:<\/h3>\n<p>Analog Circuit Designers, CAD Engineers in the Circuit Simulation Field, Engineers and Students new to Circuit Simulation.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Circuit Simulation is one of the most critical parts of the design process. Validating circuit behavior is essential to saving cost, minimize turn-around times and establishing reliable system characteristics before IC manufacture. To maximize throughput and efficiency, it is necessary to understand the internal methodologies and processes happening inside SPICE simulations. In this webinar, we [&hellip;]<\/p>\n","protected":false},"author":12,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"inline_featured_image":false,"footnotes":""},"categories":[7728],"tags":[],"class_list":["post-35940","post","type-post","status-publish","format-standard","hentry","category-spice-webinars-zh-hans","entry"],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v28.7 (Yoast SEO v28.7) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Unraveling and Optimizing Transistor-Level Simulation - Silvaco<\/title>\n<meta name=\"description\" content=\"Unraveling and Optimizing Transistor-Level Simulation\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/silvaco.com\/zh-hans\/analog-custom-design-zh-hans\/spice-zh-hans\/spice-webinars-zh-hans\/unraveling-and-optimizing-transistor-level-simulation\/\" \/>\n<meta property=\"og:locale\" content=\"zh_CN\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Unraveling and Optimizing Transistor-Level Simulation\" \/>\n<meta property=\"og:description\" content=\"Unraveling and Optimizing Transistor-Level Simulation\" \/>\n<meta property=\"og:url\" content=\"https:\/\/silvaco.com\/zh-hans\/analog-custom-design-zh-hans\/spice-zh-hans\/spice-webinars-zh-hans\/unraveling-and-optimizing-transistor-level-simulation\/\" \/>\n<meta property=\"og:site_name\" content=\"Silvaco\" \/>\n<meta property=\"article:publisher\" content=\"https:\/\/www.facebook.com\/SilvacoSoftware\/\" \/>\n<meta property=\"article:published_time\" content=\"2019-04-24T16:05:37+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2026-10-15T22:01:38+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar.jpg\" \/>\n<meta name=\"author\" content=\"Casey Molver\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:creator\" content=\"@SilvacoSoftware\" \/>\n<meta name=\"twitter:site\" content=\"@SilvacoSoftware\" \/>\n<meta name=\"twitter:label1\" content=\"\u4f5c\u8005\" \/>\n\t<meta name=\"twitter:data1\" content=\"Casey Molver\" \/>\n\t<meta name=\"twitter:label2\" content=\"\u9884\u8ba1\u9605\u8bfb\u65f6\u95f4\" \/>\n\t<meta name=\"twitter:data2\" content=\"1 minute\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\\\/\\\/silvaco.com\\\/zh-hans\\\/analog-custom-design-zh-hans\\\/spice-zh-hans\\\/spice-webinars-zh-hans\\\/unraveling-and-optimizing-transistor-level-simulation\\\/#article\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/silvaco.com\\\/zh-hans\\\/analog-custom-design-zh-hans\\\/spice-zh-hans\\\/spice-webinars-zh-hans\\\/unraveling-and-optimizing-transistor-level-simulation\\\/\"},\"author\":{\"name\":\"Casey Molver\",\"@id\":\"https:\\\/\\\/silvaco.com\\\/ja\\\/#\\\/schema\\\/person\\\/2763eb741ca5ac04477fdff50ed84c80\"},\"headline\":\"Unraveling and Optimizing Transistor-Level Simulation\",\"datePublished\":\"2019-04-24T16:05:37+00:00\",\"dateModified\":\"2026-10-15T22:01:38+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\\\/\\\/silvaco.com\\\/zh-hans\\\/analog-custom-design-zh-hans\\\/spice-zh-hans\\\/spice-webinars-zh-hans\\\/unraveling-and-optimizing-transistor-level-simulation\\\/\"},\"wordCount\":271,\"image\":{\"@id\":\"https:\\\/\\\/silvaco.com\\\/zh-hans\\\/analog-custom-design-zh-hans\\\/spice-zh-hans\\\/spice-webinars-zh-hans\\\/unraveling-and-optimizing-transistor-level-simulation\\\/#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/silvaco.com\\\/wp-content\\\/uploads\\\/2018\\\/12\\\/Webinar.jpg\",\"articleSection\":[\"SPICE Webinars\"],\"inLanguage\":\"zh-CN\"},{\"@type\":\"WebPage\",\"@id\":\"https:\\\/\\\/silvaco.com\\\/zh-hans\\\/analog-custom-design-zh-hans\\\/spice-zh-hans\\\/spice-webinars-zh-hans\\\/unraveling-and-optimizing-transistor-level-simulation\\\/\",\"url\":\"https:\\\/\\\/silvaco.com\\\/zh-hans\\\/analog-custom-design-zh-hans\\\/spice-zh-hans\\\/spice-webinars-zh-hans\\\/unraveling-and-optimizing-transistor-level-simulation\\\/\",\"name\":\"Unraveling and Optimizing Transistor-Level Simulation - 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