{"id":35905,"date":"2019-06-25T16:11:54","date_gmt":"2019-06-25T16:11:54","guid":{"rendered":"https:\/\/silvaco.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/robust-spice-modeling-with-verilog-a-principles-and-practical-techniques\/"},"modified":"2021-10-13T09:36:43","modified_gmt":"2021-10-13T16:36:43","slug":"robust-spice-modeling-with-verilog-a-principles-and-practical-techniques","status":"publish","type":"post","link":"https:\/\/silvaco.com\/zh-hans\/webinar\/robust-spice-modeling-with-verilog-a-principles-and-practical-techniques\/","title":{"rendered":"Robust SPICE Modeling with Verilog-A: Principles and Practical Techniques"},"content":{"rendered":"<div id='template_slider'  class='avia-fullwidth-slider main_color avia-shadow   avia-builder-el-0  el_before_av_section  avia-builder-el-first   container_wrap fullsize' style=' '  ><div   data-size='no scaling'  data-lightbox_size='large'  data-animation='slide'  data-conditional_play=''  data-ids='3925'  data-video_counter='0'  data-autoplay='false'  data-bg_slider='false'  data-slide_height=''  data-handle='av_slideshow_full'  data-interval='5'  data-class=' '  data-el_id=''  data-css_id=''  data-scroll_down=''  data-control_layout='av-control-default'  data-custom_markup=''  data-perma_caption=''  data-autoplay_stopper=''  data-image_attachment=''  data-min_height='110px'  data-lazy_loading='disabled'  data-src=''  data-position='top left'  data-repeat='no-repeat'  data-attach='scroll'  data-stretch=''  class='avia-slideshow avia-slideshow-1  av-control-default av-default-height-applied avia-slideshow-no scaling av_slideshow_full   avia-slide-slider '  itemprop=\"image\" itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/ImageObject\" ><ul class='avia-slideshow-inner ' style='padding-bottom: 10.46875%;' ><li  class=' av-single-slide slide-1 ' ><div data-rel='slideshow-1' class='avia-slide-wrap '   ><div class = \"caption_fullwidth av-slideshow-caption caption_bottom\"><div class = \"container caption_container\"><div class = \"slideshow_caption\"><div class = \"slideshow_inner_caption\"><div class = \"slideshow_align_caption\"><h2  style='font-size:50px; ' class='avia-caption-title   av-small-font-size-overwrite av-small-font-size-36 av-mini-font-size-overwrite av-mini-font-size-24'  itemprop=\"name\" >Webinars<\/h2><\/div><\/div><\/div><\/div><\/div><img decoding=\"async\" class=\"wp-image-18676 avia-img-lazy-loading-not-18676\"  src=\"https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar.jpg\" width=\"1920\" height=\"201\" title='Banner Blue' alt=''  itemprop=\"thumbnailUrl\"  style='min-height:110px; min-width:1051px; ' srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar.jpg 1920w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-300x31.jpg 300w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-1030x108.jpg 1030w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-768x80.jpg 768w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-1536x161.jpg 1536w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-1500x157.jpg 1500w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-705x74.jpg 705w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-43x5.jpg 43w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-63x7.jpg 63w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-48x5.jpg 48w\" sizes=\"(max-width: 1920px) 100vw, 1920px\" \/><\/div><\/li><\/ul><\/div><\/div>\n<div id='av_section_1'  class='avia-section main_color avia-section-small avia-no-border-styling  avia-bg-style-scroll  avia-builder-el-1  el_after_av_slideshow_full  avia-builder-el-last   container_wrap fullsize' style='background-color: #ffffff;  margin-top:0px; margin-bottom:0px; '  ><div class='container' ><div class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-35905'><div class='entry-content-wrapper clearfix'>\n<div class='flex_column_table av-equal-height-column-flextable -flextable' style='margin-top:20px; margin-bottom:0px; '><div class=\"flex_column av_three_fourth  flex_column_table_cell av-equal-height-column av-align-top first  avia-builder-el-2  el_before_av_one_fourth  avia-builder-el-first  \" style='padding:0px 0px 0px 0px ; border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/BlogPosting\" itemprop=\"blogPost\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1>Robust SPICE Modeling with Verilog-A: Principles and Practical Techniques<\/h1>\n<p>Insufficient robustness of models in SPICE circuit simulators may lead to a poor convergence, simulation failures and finally an unreliable or incorrect circuit design. Implementation of these compact models, including the responsibility to ensure robust behavior, were traditionally left to the expertise of EDA vendors. However, with the introduction and wide adoption of Verilog-A as a model coding language in analog circuit simulators, the power of the model implementation is now available to the circuit designers and SPICE circuit simulator users. It has also brought an unaccustomed responsibility to circuit designers and model developers to ensure robustness of the implemented model. The main goal of this webinar is to present an expert guidance for robust coding of SPICE compact models in Verilog-A.<\/p>\n<h2>What attendees will learn:<\/h2>\n<ul id=\"web-bullet\">\n<li>Basic principles and best practices for ensuring robustness of SPICE compact models coded in Verilog-A.<\/li>\n<li>How to avoid floating point exceptions and real number related issues in model evaluation and hidden evaluation of model code derivatives.<\/li>\n<li>How to provide required continuity of a model behavioral description using smoothing, limiting and transition functions.<\/li>\n<li>Practical techniques for improving SPICE convergence robustness in circuit simulations with Verilog-A models.<\/li>\n<\/ul>\n<\/div><\/section><br \/>\n<div   class='hr hr-default   avia-builder-el-4  el_after_av_textblock  el_before_av_textblock '><span class='hr-inner ' ><span class='hr-inner-style'><\/span><\/span><\/div><br \/>\n<section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/BlogPosting\" itemprop=\"blogPost\" ><div class='avia_textblock  '   itemprop=\"text\" ><h2>Presenter<\/h2>\n<\/div><\/section><br \/>\n<section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/BlogPosting\" itemprop=\"blogPost\" ><div class='avia_textblock  '   itemprop=\"text\" ><p><img loading=\"lazy\" decoding=\"async\" class=\"alignleft wp-image-1268 size-full\" src=\"\/wp-content\/uploads\/2020\/01\/slobodan.jpg\" alt=\"Dr. Slobodan Mijalkovic\" width=\"100\" height=\"100\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/01\/slobodan.jpg 100w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/01\/slobodan-80x80.jpg 80w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/01\/slobodan-36x36.jpg 36w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/01\/slobodan-37x37.jpg 37w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/01\/slobodan-55x55.jpg 55w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/01\/slobodan-48x48.jpg 48w\" sizes=\"(max-width: 100px) 100vw, 100px\" \/>Dr. Slobodan Mijalkovic is a Senior R&amp;D Engineer at Silvaco specialized in compact model development and implementation in circuit simulation tools. Before joining Silvaco, he was a Principal Researcher at Delft University of Technology in the Netherlands, where he has led a team for standardization of the Mextram bipolar transistor model with Compact Model Coalition (CMC). He is a member of IEEE EDS Compact Modeling Committee.<\/p>\n<\/div><\/section><br \/>\n<div   class='hr hr-default   avia-builder-el-7  el_after_av_textblock  avia-builder-el-last '><span class='hr-inner ' ><span class='hr-inner-style'><\/span><\/span><\/div><\/p><\/div><div class='av-flex-placeholder'><\/div><div class=\"flex_column av_one_fourth  flex_column_table_cell av-equal-height-column av-align-top   avia-builder-el-8  el_after_av_three_fourth  avia-builder-el-last  \" style='padding:0px 0px 0px 0px ; border-radius:0px; '><p><section class=\"av_textblock_section \"  id=\"date\"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/BlogPosting\" itemprop=\"blogPost\" ><div class='avia_textblock  '   itemprop=\"text\" ><p><strong>When<\/strong>: June 25, 2019<br \/>\n<strong>Where<\/strong>: Online<br \/>\n<strong>Time<\/strong>: 10:00am-11:00am-(PST)<br \/>\n<strong>Language<\/strong>: English<\/p>\n<\/div><\/section><br \/>\n<div   class='hr hr-default   avia-builder-el-10  el_after_av_textblock  el_before_av_button '><span class='hr-inner ' ><span class='hr-inner-style'><\/span><\/span><\/div><br \/>\n<div  class='avia-button-wrap avia-button-center  avia-builder-el-11  el_after_av_hr  el_before_av_hr ' ><a href='\/dynamicweb\/jsp\/downloads\/DownloadDocStepsAction.do?req=silen-download&amp;nm=Robust_SPICE_Modeling_with_Verilog_A_Principles_Practical_Techniques.mp4&amp;prefixname=video'  class='avia-button  avia-color-grey   avia-icon_select-no avia-size-small avia-position-center '   ><span class='avia_iconbox_title' >Register to View Archive<\/span><\/a><\/div><br \/>\n<div   class='hr hr-default   avia-builder-el-12  el_after_av_button  el_before_av_textblock '><span class='hr-inner ' ><span class='hr-inner-style'><\/span><\/span><\/div><br \/>\n<section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/BlogPosting\" itemprop=\"blogPost\" ><div class='avia_textblock  '   itemprop=\"text\" ><h3>WHO SHOULD ATTEND:<\/h3>\n<\/div><\/section><br \/>\n<section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/BlogPosting\" itemprop=\"blogPost\" ><div class='avia_textblock  '   itemprop=\"text\" ><p>Circuit designers and model developing experts in academia and industry who are coding SPICE compact models in the Verilog-A language.<\/p>\n<\/div><\/section><\/p><\/div><\/div><!--close column table wrapper. Autoclose: 1 -->\n","protected":false},"excerpt":{"rendered":"","protected":false},"author":5,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[7730,7728],"tags":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v24.0 (Yoast SEO v24.0) - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Robust SPICE Modeling with Verilog-A: Principles and Practical Techniques - Silvaco<\/title>\n<meta name=\"description\" content=\"Insufficient robustness of models in SPICE circuit simulators may lead to a poor convergence, simulation failures and finally an unreliable\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/silvaco.com\/zh-hans\/webinar\/robust-spice-modeling-with-verilog-a-principles-and-practical-techniques\/\" \/>\n<meta property=\"og:locale\" content=\"zh_CN\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Robust SPICE Modeling with Verilog-A: Principles and Practical Techniques\" \/>\n<meta property=\"og:description\" content=\"Insufficient robustness of models in SPICE circuit simulators may lead to a poor convergence, simulation failures and finally an unreliable\" \/>\n<meta property=\"og:url\" content=\"https:\/\/silvaco.com\/zh-hans\/webinar\/robust-spice-modeling-with-verilog-a-principles-and-practical-techniques\/\" \/>\n<meta property=\"og:site_name\" content=\"Silvaco\" \/>\n<meta property=\"article:publisher\" content=\"https:\/\/www.facebook.com\/SilvacoSoftware\/\" \/>\n<meta property=\"article:published_time\" content=\"2019-06-25T16:11:54+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2021-10-13T16:36:43+00:00\" \/>\n<meta name=\"author\" content=\"Ingrid Schwarz\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:creator\" content=\"@SilvacoSoftware\" \/>\n<meta name=\"twitter:site\" content=\"@SilvacoSoftware\" \/>\n<meta name=\"twitter:label1\" content=\"\u4f5c\u8005\" \/>\n\t<meta name=\"twitter:data1\" content=\"Ingrid Schwarz\" \/>\n\t<meta name=\"twitter:label2\" content=\"\u9884\u8ba1\u9605\u8bfb\u65f6\u95f4\" \/>\n\t<meta name=\"twitter:data2\" content=\"7 \u5206\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"WebPage\",\"@id\":\"https:\/\/silvaco.com\/zh-hans\/webinar\/robust-spice-modeling-with-verilog-a-principles-and-practical-techniques\/\",\"url\":\"https:\/\/silvaco.com\/zh-hans\/webinar\/robust-spice-modeling-with-verilog-a-principles-and-practical-techniques\/\",\"name\":\"Robust SPICE Modeling with Verilog-A: Principles and Practical Techniques - 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