{"id":35905,"date":"2019-06-25T16:11:54","date_gmt":"2019-06-25T16:11:54","guid":{"rendered":"https:\/\/silvaco.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/robust-spice-modeling-with-verilog-a-principles-and-practical-techniques\/"},"modified":"2026-10-15T15:01:41","modified_gmt":"2026-10-15T22:01:41","slug":"robust-spice-modeling-with-verilog-a-principles-and-practical-techniques","status":"publish","type":"post","link":"https:\/\/silvaco.com\/zh-hans\/analog-custom-design-zh-hans\/spice-zh-hans\/spice-webinars-zh-hans\/robust-spice-modeling-with-verilog-a-principles-and-practical-techniques\/","title":{"rendered":"Robust SPICE Modeling with Verilog-A: Principles and Practical Techniques"},"content":{"rendered":"

\"Banner<\/p>\n

Insufficient robustness of models in SPICE circuit simulators may lead to a poor convergence, simulation failures and finally an unreliable or incorrect circuit design. Implementation of these compact models, including the responsibility to ensure robust behavior, were traditionally left to the expertise of EDA vendors. However, with the introduction and wide adoption of Verilog-A as a model coding language in analog circuit simulators, the power of the model implementation is now available to the circuit designers and SPICE circuit simulator users. It has also brought an unaccustomed responsibility to circuit designers and model developers to ensure robustness of the implemented model. The main goal of this webinar is to present an expert guidance for robust coding of SPICE compact models in Verilog-A.<\/p>\n

What attendees will learn:<\/h2>\n