{"id":35864,"date":"2019-10-24T00:00:20","date_gmt":"2019-10-24T00:00:20","guid":{"rendered":"https:\/\/silvaco.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/ai-and-machine-learning-socs-memory-and-interconnect-ip-perspectives\/"},"modified":"2021-10-13T09:32:02","modified_gmt":"2021-10-13T16:32:02","slug":"ai-and-machine-learning-socs-memory-and-interconnect-ip-perspectives","status":"publish","type":"post","link":"https:\/\/silvaco.com\/zh-hans\/webinar\/ai-and-machine-learning-socs-memory-and-interconnect-ip-perspectives\/","title":{"rendered":"AI and Machine Learning SoCs \u2013 Memory and Interconnect IP Perspectives"},"content":{"rendered":"<div id='template_slider'  class='avia-fullwidth-slider main_color avia-shadow   avia-builder-el-0  el_before_av_section  avia-builder-el-first   container_wrap fullsize' style=' '  ><div   data-size='no scaling'  data-lightbox_size='large'  data-animation='slide'  data-conditional_play=''  data-ids='3925'  data-video_counter='0'  data-autoplay='false'  data-bg_slider='false'  data-slide_height=''  data-handle='av_slideshow_full'  data-interval='5'  data-class=' '  data-el_id=''  data-css_id=''  data-scroll_down=''  data-control_layout='av-control-default'  data-custom_markup=''  data-perma_caption=''  data-autoplay_stopper=''  data-image_attachment=''  data-min_height='110px'  data-lazy_loading='disabled'  data-src=''  data-position='top left'  data-repeat='no-repeat'  data-attach='scroll'  data-stretch=''  class='avia-slideshow avia-slideshow-1  av-control-default av-default-height-applied avia-slideshow-no scaling av_slideshow_full   avia-slide-slider '  itemprop=\"image\" itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/ImageObject\" ><ul class='avia-slideshow-inner ' style='padding-bottom: 10.46875%;' ><li  class=' av-single-slide slide-1 ' ><div data-rel='slideshow-1' class='avia-slide-wrap '   ><div class = \"caption_fullwidth av-slideshow-caption caption_bottom\"><div class = \"container caption_container\"><div class = \"slideshow_caption\"><div class = \"slideshow_inner_caption\"><div class = \"slideshow_align_caption\"><h2  style='font-size:50px; ' class='avia-caption-title   av-small-font-size-overwrite av-small-font-size-36 av-mini-font-size-overwrite av-mini-font-size-24'  itemprop=\"name\" >Webinars<\/h2><\/div><\/div><\/div><\/div><\/div><img decoding=\"async\" class=\"wp-image-18676 avia-img-lazy-loading-not-18676\"  src=\"https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar.jpg\" width=\"1920\" height=\"201\" title='Banner Blue' alt=''  itemprop=\"thumbnailUrl\"  style='min-height:110px; min-width:1051px; ' srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar.jpg 1920w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-300x31.jpg 300w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-1030x108.jpg 1030w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-768x80.jpg 768w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-1536x161.jpg 1536w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-1500x157.jpg 1500w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-705x74.jpg 705w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-43x5.jpg 43w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-63x7.jpg 63w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-48x5.jpg 48w\" sizes=\"(max-width: 1920px) 100vw, 1920px\" \/><\/div><\/li><\/ul><\/div><\/div>\n<div id='av_section_1'  class='avia-section main_color avia-section-small avia-no-border-styling  avia-bg-style-scroll  avia-builder-el-1  el_after_av_slideshow_full  avia-builder-el-last   container_wrap fullsize' style='background-color: #ffffff;  margin-top:0px; margin-bottom:0px; '  ><div class='container' ><div class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-35864'><div class='entry-content-wrapper clearfix'>\n<div class='flex_column_table av-equal-height-column-flextable -flextable' style='margin-top:20px; margin-bottom:0px; '><div class=\"flex_column av_three_fourth  flex_column_table_cell av-equal-height-column av-align-top first  avia-builder-el-2  el_before_av_one_fourth  avia-builder-el-first  \" style='padding:0px 0px 0px 0px ; border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/BlogPosting\" itemprop=\"blogPost\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1>AI and Machine Learning SoCs \u2013 Memory and Interconnect IP Perspectives<\/h1>\n<p>This webinar will discuss the challenges of developing of artificial intelligence (AI) and machine learning (ML) based SoCs. Novel architectures for AI and ML applications are needed to meet efficiency requirements. These include specialized processing, high bandwidth and low-energy memory throughput, and reliable high-performance connectivity. We will present the efficient customization of memory and interconnect IPs for successful development of AI and ML SoCs.<\/p>\n<h2>What attendees will learn:<\/h2>\n<ul id=\"web-bullet\">\n<li>Challenges of AI\/ML SoCs<\/li>\n<li>Key requirements of Memory and Interconnect IPs for AI\/ML SoCs<\/li>\n<li>Memory and interconnect SIPware solutions by Silvaco<\/li>\n<\/ul>\n<\/div><\/section><br \/>\n<div   class='hr hr-default   avia-builder-el-4  el_after_av_textblock  el_before_av_textblock '><span class='hr-inner ' ><span class='hr-inner-style'><\/span><\/span><\/div><br \/>\n<section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/BlogPosting\" itemprop=\"blogPost\" ><div class='avia_textblock  '   itemprop=\"text\" ><h2>Presenter<\/h2>\n<\/div><\/section><br \/>\n<section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/BlogPosting\" itemprop=\"blogPost\" ><div class='avia_textblock  '   itemprop=\"text\" ><p><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-4107 size-full alignleft\" src=\"\/wp-content\/uploads\/2020\/02\/ahmad.jpg\" alt=\"\" width=\"100\" height=\"100\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/ahmad.jpg 100w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/ahmad-80x80.jpg 80w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/ahmad-36x36.jpg 36w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/ahmad-37x37.jpg 37w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/ahmad-55x55.jpg 55w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/ahmad-48x48.jpg 48w\" sizes=\"(max-width: 100px) 100vw, 100px\" \/><\/p>\n<p>Ahmad S. Mazumder is a principal field application engineer in IP Engineering division of Silvaco. He is responsible for development and customer support in all analog and interface IPs. He is an industry veteran on the development of high-speed memory, interface IPs, and many types of analog IPs. He worked on cutting edge DDR, extreme high-speed SerDes, interfaces, ESD, and QoR for 24 years at various SoC companies (Intel, Broadcom, C-Cube Microsystems, etc). He recently joined Silvaco\u2019s IP Engineering division.<\/p>\n<p>Ahmad S. Mazumder holds a MS in VLSI Semiconductor Design from the City University of New York and BS in Electrical and Electronics Engineering from Bangladesh University of Engineering and Technology.<\/p>\n<\/div><\/section><br \/>\n<div   class='hr hr-default   avia-builder-el-7  el_after_av_textblock  avia-builder-el-last '><span class='hr-inner ' ><span class='hr-inner-style'><\/span><\/span><\/div><\/p><\/div><div class='av-flex-placeholder'><\/div><div class=\"flex_column av_one_fourth  flex_column_table_cell av-equal-height-column av-align-top   avia-builder-el-8  el_after_av_three_fourth  avia-builder-el-last  \" style='padding:0px 0px 0px 0px ; border-radius:0px; '><p><section class=\"av_textblock_section \"  id=\"date\"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/BlogPosting\" itemprop=\"blogPost\" ><div class='avia_textblock  '   itemprop=\"text\" ><p><strong>When<\/strong>: December 6, 2018<br \/>\n<strong>Where<\/strong>: Online<br \/>\n<strong>Time<\/strong>: 10:00am-11:00am &#8211; (PST)<br \/>\n<strong>Language<\/strong>: English<\/p>\n<\/div><\/section><br \/>\n<div   class='hr hr-default   avia-builder-el-10  el_after_av_textblock  el_before_av_button '><span class='hr-inner ' ><span class='hr-inner-style'><\/span><\/span><\/div><br \/>\n<div  class='avia-button-wrap avia-button-center  avia-builder-el-11  el_after_av_hr  el_before_av_hr ' ><a href='\/dynamicweb\/jsp\/downloads\/DownloadDocStepsAction.do?req=silen-download&amp;nm=AI_and_Machine_Learning_SoCs.mp4&amp;prefixname=video'  class='avia-button  avia-color-grey   avia-icon_select-no avia-size-small avia-position-center '   ><span class='avia_iconbox_title' >Register to View Archive<\/span><\/a><\/div><br \/>\n<div   class='hr hr-default   avia-builder-el-12  el_after_av_button  el_before_av_textblock '><span class='hr-inner ' ><span class='hr-inner-style'><\/span><\/span><\/div><br \/>\n<section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/BlogPosting\" itemprop=\"blogPost\" ><div class='avia_textblock  '   itemprop=\"text\" ><h3>WHO SHOULD ATTEND:<\/h3>\n<\/div><\/section><br \/>\n<section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/BlogPosting\" itemprop=\"blogPost\" ><div class='avia_textblock  '   itemprop=\"text\" ><p>Academics, engineers, and management looking for solutions to design and optimize artificial intelligence and machine learning SoCs.<\/p>\n<\/div><\/section><\/p><\/div><\/div><!--close column table wrapper. Autoclose: 1 -->\n","protected":false},"excerpt":{"rendered":"","protected":false},"author":3,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[7726],"tags":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v24.0 (Yoast SEO v24.0) - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>AI and Machine Learning SoCs \u2013 Memory and Interconnect IP Perspectives - Silvaco<\/title>\n<meta name=\"description\" content=\"AI and Machine Learning SoCs \u2013 Memory and Interconnect IP Perspectives\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/silvaco.com\/zh-hans\/webinar\/ai-and-machine-learning-socs-memory-and-interconnect-ip-perspectives\/\" \/>\n<meta property=\"og:locale\" content=\"zh_CN\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"AI and Machine Learning SoCs \u2013 Memory and Interconnect IP Perspectives\" \/>\n<meta property=\"og:description\" content=\"AI and Machine Learning SoCs \u2013 Memory and Interconnect IP Perspectives\" \/>\n<meta property=\"og:url\" content=\"https:\/\/silvaco.com\/zh-hans\/webinar\/ai-and-machine-learning-socs-memory-and-interconnect-ip-perspectives\/\" \/>\n<meta property=\"og:site_name\" content=\"Silvaco\" \/>\n<meta property=\"article:publisher\" content=\"https:\/\/www.facebook.com\/SilvacoSoftware\/\" \/>\n<meta property=\"article:published_time\" content=\"2019-10-24T00:00:20+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2021-10-13T16:32:02+00:00\" \/>\n<meta name=\"author\" content=\"Erick Castellon\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:creator\" content=\"@SilvacoSoftware\" \/>\n<meta name=\"twitter:site\" content=\"@SilvacoSoftware\" \/>\n<meta name=\"twitter:label1\" content=\"\u4f5c\u8005\" \/>\n\t<meta name=\"twitter:data1\" content=\"Erick Castellon\" \/>\n\t<meta name=\"twitter:label2\" content=\"\u9884\u8ba1\u9605\u8bfb\u65f6\u95f4\" \/>\n\t<meta name=\"twitter:data2\" content=\"6 \u5206\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"WebPage\",\"@id\":\"https:\/\/silvaco.com\/zh-hans\/webinar\/ai-and-machine-learning-socs-memory-and-interconnect-ip-perspectives\/\",\"url\":\"https:\/\/silvaco.com\/zh-hans\/webinar\/ai-and-machine-learning-socs-memory-and-interconnect-ip-perspectives\/\",\"name\":\"AI and Machine Learning SoCs \u2013 Memory and Interconnect IP Perspectives - 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