{"id":35853,"date":"2019-11-21T21:22:24","date_gmt":"2019-11-21T21:22:24","guid":{"rendered":"https:\/\/silvaco.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/optimization-of-the-select-gate-transistor-in-a-3d-nand-memory-cell\/"},"modified":"2021-10-13T09:31:42","modified_gmt":"2021-10-13T16:31:42","slug":"optimization-of-the-select-gate-transistor-in-a-3d-nand-memory-cell","status":"publish","type":"post","link":"https:\/\/silvaco.com\/zh-hans\/tcad-zh-hans\/tcad-webinars-zh-hans\/optimization-of-the-select-gate-transistor-in-a-3d-nand-memory-cell\/","title":{"rendered":"Optimization of the Select Gate Transistor in a 3D NAND Memory Cell"},"content":{"rendered":"<div id='template_slider'  class='avia-fullwidth-slider main_color avia-shadow   avia-builder-el-0  el_before_av_section  avia-builder-el-first   container_wrap fullsize' style=' '  ><div   data-size='no scaling'  data-lightbox_size='large'  data-animation='slide'  data-conditional_play=''  data-ids='3925'  data-video_counter='0'  data-autoplay='false'  data-bg_slider='false'  data-slide_height=''  data-handle='av_slideshow_full'  data-interval='5'  data-class=' '  data-el_id=''  data-css_id=''  data-scroll_down=''  data-control_layout='av-control-default'  data-custom_markup=''  data-perma_caption=''  data-autoplay_stopper=''  data-image_attachment=''  data-min_height='110px'  data-lazy_loading='disabled'  data-src=''  data-position='top left'  data-repeat='no-repeat'  data-attach='scroll'  data-stretch=''  class='avia-slideshow avia-slideshow-1  av-control-default av-default-height-applied avia-slideshow-no scaling av_slideshow_full   avia-slide-slider '  itemprop=\"image\" itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/ImageObject\" ><ul class='avia-slideshow-inner ' style='padding-bottom: 10.46875%;' ><li  class=' av-single-slide slide-1 ' ><div data-rel='slideshow-1' class='avia-slide-wrap '   ><div class = \"caption_fullwidth av-slideshow-caption caption_bottom\"><div class = \"container caption_container\"><div class = \"slideshow_caption\"><div class = \"slideshow_inner_caption\"><div class = \"slideshow_align_caption\"><h2  style='font-size:50px; ' class='avia-caption-title   av-small-font-size-overwrite av-small-font-size-36 av-mini-font-size-overwrite av-mini-font-size-24'  itemprop=\"name\" >Webinars<\/h2><\/div><\/div><\/div><\/div><\/div><img decoding=\"async\" class=\"wp-image-18676 avia-img-lazy-loading-not-18676\"  src=\"https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar.jpg\" width=\"1920\" height=\"201\" title='Banner Blue' alt=''  itemprop=\"thumbnailUrl\"  style='min-height:110px; min-width:1051px; ' srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar.jpg 1920w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-300x31.jpg 300w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-1030x108.jpg 1030w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-768x80.jpg 768w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-1536x161.jpg 1536w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-1500x157.jpg 1500w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-705x74.jpg 705w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-43x5.jpg 43w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-63x7.jpg 63w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-48x5.jpg 48w\" sizes=\"(max-width: 1920px) 100vw, 1920px\" \/><\/div><\/li><\/ul><\/div><\/div>\n<div id='av_section_1'  class='avia-section main_color avia-section-small avia-no-border-styling  avia-bg-style-scroll  avia-builder-el-1  el_after_av_slideshow_full  avia-builder-el-last   container_wrap fullsize' style='background-color: #ffffff;  margin-top:0px; margin-bottom:0px; '  ><div class='container' ><div class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-35853'><div class='entry-content-wrapper clearfix'>\n<div class='flex_column_table av-equal-height-column-flextable -flextable' style='margin-top:20px; margin-bottom:0px; '><div class=\"flex_column av_three_fourth  flex_column_table_cell av-equal-height-column av-align-top first  avia-builder-el-2  el_before_av_one_fourth  avia-builder-el-first  \" style='padding:0px 0px 0px 0px ; border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/BlogPosting\" itemprop=\"blogPost\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1>Optimization of the Select Gate Transistor in a 3D NAND Memory Cell<\/h1>\n<p>This webinar will present the usage of TCAD process and device software for optimizing the operation of a 3D NAND memory cell with a focus on the select gate transistor. There are several design requirements specific to the select gate transistor in a 3D NAND memory cell. Low leakage current is needed to prevent memory read and program disturb errors that cause a shift in the threshold voltage of adjacent memory cells. Additionally, during memory read and erase operations, the gate transistor needs to provide enough current to drive the memory cells. In this webinar, we examine the design optimization of the select gate transistor with respect to various device elements including work function, source\/drain overlap, and trap density. Finally, we cover reducing the channel length of the select gate transistor with respect to the use of dummy memory cells for threshold voltage control.<\/p>\n<h2>What attendees will learn:<\/h2>\n<ul id=\"web-bullet\">\n<li>Challenges of 3D NAND scaling<\/li>\n<li>Requirements for a 3D NAND select gate transistor<\/li>\n<li>TCAD simulation of 3D NAND cell operations\n<ul>\n<li>Read\/program operation<\/li>\n<li>Erase operation<\/li>\n<li>Program disturb error<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/div><\/section><br \/>\n<div  style='background:#c7e1e5;color:#595959;border-color:#e0e0e0;' class='av_promobox  avia-button-yes   avia-builder-el-4  el_after_av_textblock  el_before_av_hr '><div class='avia-promocontent'><\/p>\n<h3>To view our webinar register to view content.<\/h3>\n<p>\n<\/div><div  class='avia-button-wrap avia-button-right ' ><a href='\/dynamicweb\/jsp\/downloads\/DownloadDocStepsAction.do?req=silen-download&amp;nm=Optimization_Select_Gate_Transistor_in_3D_NAND_Memory_Cell.mp4&amp;prefixname=video'  class='avia-button  avia-color-grey   avia-icon_select-no avia-size-medium avia-position-right '   ><span class='avia_iconbox_title' >Register to View Archive<\/span><\/a><\/div><\/div><br \/>\n<div   class='hr hr-default   avia-builder-el-5  el_after_av_promobox  el_before_av_textblock '><span class='hr-inner ' ><span class='hr-inner-style'><\/span><\/span><\/div><br \/>\n<section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/BlogPosting\" itemprop=\"blogPost\" ><div class='avia_textblock  '   itemprop=\"text\" ><h2>Presenter<\/h2>\n<\/div><\/section><br \/>\n<section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/BlogPosting\" itemprop=\"blogPost\" ><div class='avia_textblock  '   itemprop=\"text\" ><div>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-4582 alignleft\" src=\"\/wp-content\/uploads\/2020\/02\/Cho2.jpg\" alt=\"\" width=\"120\" height=\"120\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/Cho2.jpg 120w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/Cho2-80x80.jpg 80w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/Cho2-36x36.jpg 36w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/Cho2-37x37.jpg 37w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/Cho2-55x55.jpg 55w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/Cho2-48x48.jpg 48w\" sizes=\"(max-width: 120px) 100vw, 120px\" \/>Dr. Jin Cho is Principal Application Engineer at Silvaco, based in Santa Clara, USA. Prior to joining Silvaco in 2018, he was with GLOBALFOUNDRIES\/AMD for 15 years where he held the position of process\/device manager of 14\/10nm logic technology development and managed TCAD group for future device technology research. Jin holds a Ph. D. from Stanford University.<\/p>\n<\/div>\n<\/div><\/section><br \/>\n<div   class='hr hr-default   avia-builder-el-8  el_after_av_textblock  avia-builder-el-last '><span class='hr-inner ' ><span class='hr-inner-style'><\/span><\/span><\/div><\/p><\/div><div class='av-flex-placeholder'><\/div><div class=\"flex_column av_one_fourth  flex_column_table_cell av-equal-height-column av-align-top   avia-builder-el-9  el_after_av_three_fourth  avia-builder-el-last  \" style='padding:0px 0px 0px 0px ; border-radius:0px; '><p><section class=\"av_textblock_section \"  id=\"date\"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/BlogPosting\" itemprop=\"blogPost\" ><div class='avia_textblock  '   itemprop=\"text\" ><p><strong>When<\/strong>: November 21, 2019<br \/>\n<strong>Where<\/strong>: Online<br \/>\n<strong>Time<\/strong>: 10:00am-11:00am &#8211; (PST)<br \/>\n<strong>Language<\/strong>: English<\/p>\n<\/div><\/section><br \/>\n<div   class='hr hr-default   avia-builder-el-11  el_after_av_textblock  el_before_av_button '><span class='hr-inner ' ><span class='hr-inner-style'><\/span><\/span><\/div><br \/>\n<div  class='avia-button-wrap avia-button-center  avia-builder-el-12  el_after_av_hr  el_before_av_hr ' ><a href='\/dynamicweb\/jsp\/downloads\/DownloadDocStepsAction.do?req=silen-download&amp;nm=Optimization_Select_Gate_Transistor_in_3D_NAND_Memory_Cell.mp4&amp;prefixname=video'  class='avia-button  avia-color-grey   avia-icon_select-no avia-size-small avia-position-center '   ><span class='avia_iconbox_title' >Register to View Archive<\/span><\/a><\/div><br \/>\n<div   class='hr hr-default   avia-builder-el-13  el_after_av_button  el_before_av_textblock '><span class='hr-inner ' ><span class='hr-inner-style'><\/span><\/span><\/div><br \/>\n<section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/BlogPosting\" itemprop=\"blogPost\" ><div class='avia_textblock  '   itemprop=\"text\" ><h3>WHO SHOULD ATTEND:<\/h3>\n<\/div><\/section><br \/>\n<section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/BlogPosting\" itemprop=\"blogPost\" ><div class='avia_textblock  '   itemprop=\"text\" ><div class=\"col-md-7\">\n<div>\n<p>Academics, engineers, and management looking for solutions to design and optimize 3D NAND cell operation.<\/p>\n<\/div>\n<\/div>\n<div class=\"col-md-3\">\n<aside class=\"sidebar\">\n<div id=\"side\">\n<div><\/div>\n<\/div>\n<\/aside>\n<\/div>\n<\/div><\/section><\/p><\/div><\/div><!--close column table wrapper. Autoclose: 1 -->\n","protected":false},"excerpt":{"rendered":"","protected":false},"author":5,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[7729],"tags":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v24.0 (Yoast SEO v24.0) - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Optimization of the Select Gate Transistor in a 3D NAND Memory Cell - Silvaco<\/title>\n<meta name=\"description\" content=\"This webinar will present the usage of TCAD process and device software for optimizing the operation of a 3D NAND memory\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/silvaco.com\/zh-hans\/tcad-zh-hans\/tcad-webinars-zh-hans\/optimization-of-the-select-gate-transistor-in-a-3d-nand-memory-cell\/\" \/>\n<meta property=\"og:locale\" content=\"zh_CN\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Optimization of the Select Gate Transistor in a 3D NAND Memory Cell\" \/>\n<meta property=\"og:description\" content=\"This webinar will present the usage of TCAD process and device software for optimizing the operation of a 3D NAND memory\" \/>\n<meta property=\"og:url\" content=\"https:\/\/silvaco.com\/zh-hans\/tcad-zh-hans\/tcad-webinars-zh-hans\/optimization-of-the-select-gate-transistor-in-a-3d-nand-memory-cell\/\" \/>\n<meta property=\"og:site_name\" content=\"Silvaco\" \/>\n<meta property=\"article:publisher\" content=\"https:\/\/www.facebook.com\/SilvacoSoftware\/\" \/>\n<meta property=\"article:published_time\" content=\"2019-11-21T21:22:24+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2021-10-13T16:31:42+00:00\" \/>\n<meta name=\"author\" content=\"Ingrid Schwarz\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:creator\" content=\"@SilvacoSoftware\" \/>\n<meta name=\"twitter:site\" content=\"@SilvacoSoftware\" \/>\n<meta name=\"twitter:label1\" content=\"\u4f5c\u8005\" \/>\n\t<meta name=\"twitter:data1\" content=\"Ingrid Schwarz\" \/>\n\t<meta name=\"twitter:label2\" content=\"\u9884\u8ba1\u9605\u8bfb\u65f6\u95f4\" \/>\n\t<meta name=\"twitter:data2\" content=\"7 \u5206\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"WebPage\",\"@id\":\"https:\/\/silvaco.com\/zh-hans\/tcad-zh-hans\/tcad-webinars-zh-hans\/optimization-of-the-select-gate-transistor-in-a-3d-nand-memory-cell\/\",\"url\":\"https:\/\/silvaco.com\/zh-hans\/tcad-zh-hans\/tcad-webinars-zh-hans\/optimization-of-the-select-gate-transistor-in-a-3d-nand-memory-cell\/\",\"name\":\"Optimization of the Select Gate Transistor in a 3D NAND Memory Cell - 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