{"id":35823,"date":"2020-02-26T19:12:19","date_gmt":"2020-02-26T19:12:19","guid":{"rendered":"https:\/\/silvaco.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/nanoscale-devices\/"},"modified":"2020-02-26T19:12:19","modified_gmt":"2020-02-26T19:12:19","slug":"nanoscale-devices","status":"publish","type":"post","link":"https:\/\/silvaco.com\/zh-hans\/tcad-zh-hans\/tcad-published-papers-zh-hans\/nanoscale-devices-zh-hans\/nanoscale-devices\/","title":{"rendered":"Nanoscale Devices"},"content":{"rendered":"
\n

Nanoscale Devices<\/h1>\n

The full text for most of these papers may be found at the IEEE website at\u00a0www.ieee.org<\/a>.<\/p>\n

P. Blaise,1,2<\/sup>
\n“Ab Initio Simulation of Advanced Materials and Devices: Current Challenges<\/a>“,
\n1<\/sup>Silvaco Montbonnot, 38330, France
\n2<\/sup>Univ. Grenoble Alpes, CEA, LETI, 38000 Grenoble, France.<\/p>\n

Zhenqiang Ma, Guoxuan Qin,
\n“Fast Flexible Electronics Made from Nanomembranes Derived from High-Quality Wafers”,
\nSemiconductor Nanomaterials for Flexible Technologies, 2010, pp. 67-104.<\/p>\n

D.H. Tassis, A. Tsormpatzoglou, C.A. Dimitriadis, G. Ghibaudo, G. Pananakakis, N. Collaert,
\n“Source\/drain optimization of underlapped lightly doped nanoscale double-gate MOSFETs”,
\nMicroelectronic Engineering, Vol. 87, Issue 11, November 2010, pp. 2353-2357.<\/p>\n

Guriqbal Singh Josan, Archana Devasia, Sean Rommel, Santosh K. Kurinec,
\n“Simulation and verification of void transfer patterning (VTP) technique for nm-scale features”,
\nMicroelectronic Engineering, In Press, Corrected Proof, Available online 27 August 2010.<\/p>\n

Ping Bai, Hong Son Chu, Mingxia Gu, Oka Kurniawan, Erping Li,
\n“Integration of plasmonics into nanoelectronic circuits”,
\nPhysica B: Condensed Matter, Vol. 405, Issue 14, 15 July 2010, pp. 2978-2981.<\/p>\n

Seong-Wan Ryu, Chang-Hoon Kim, Jin-Woo Han, Chung-Jin Kim, Cheulhee Jung, Hyun Gyu Park, Yang-Kyu Choi,
\n“Gold nanoparticle embedded silicon nanowire biosensor for applications of label-free DNA detection”,
\nBiosensors and Bioelectronics, Vol. 25, Issue 9, 15 May 2010, pp. 2182-2185.<\/p>\n

Oka Kurniawan, Man-Fai Ng, Wee Shing Koh, Zuan Yi Leong, Erping Li,
\n“Simplified model for ballistic current\u2013voltage characteristic in cylindrical nanowires”,
\nMicroelectronics Journal, Vol. 41, Issues 2-3, February-March 2010, pp. 155-161.<\/p>\n

F. Djeffal, M. Meguellati, A. Benhaya,
\n“A two-dimensional analytical analysis of subthreshold behavior to study the scaling capability of nanoscale graded channel gate stack DG MOSFETs”,
\nPhysica E: Low-dimensional Systems and Nanostructures, Vol. 41, Issue 10, October 2009, pp. 1872-1877.<\/p>\n

U. Monga, H. B\u00f8rli, T. A. Fjeldly,
\n“Compact subthreshold current and capacitance modeling of short-channel double-gate MOSFETs”,
\nMathematical and Computer Modelling, In Press, Accepted Manuscript, Available online 30 September 2009.<\/p>\n

Zhigong Wang, Xiaosong Gu, Xiaoying L\u00fc, Zhenglin Jiang, Wenyuan Li, Guangming L\u00fc, Yufeng Wang, Xiaoyan Shen, Xintai Zhao, Huiling Wang, Zhenyu Zhang, Hongmei Shen, Yang Wu, Weixing Shen, Jingyang Zhang, Dong Chen, Xiaoyi Mao, Huaxiang Shen,
\n“Microelectronics-embedded channel bridging and signal regeneration of injured spinal cords”,
\nProgress in Natural Science, Vol. 19, Issue 10, 10 October 2009, pp. 1261-1269.<\/p>\n

Servin Rathi, Jyotika Jogi, Mridula Gupta, R.S. Gupta,
\n“Modeling of hetero-interface potential and threshold voltage for tied and separate nanoscale InAlAs\u2013InGaAs symmetric double-gate HEMT”,
\nMicroelectronics Reliability, In Press, Corrected Proof, Available online 11 August 2009.<\/p>\n

X. Loussier, D. Munteanu, J. L. Autran,
\n“Simulation study of circuit performances of independent double-gate (IDG) MOSFETs with high-permittivity gate dielectrics”,
\nJournal of Non-Crystalline Solids, Vol. 355, Issues 18-21, 1 July 2009, pp. 1185-1188.<\/p>\n

Ren\u00e9 Pinnau, Jorge Mauricio Ruiz V,
\n“Convergent finite element discretizations of the density gradient equation for quantum semiconductors”,
\nJournal of Computational and Applied Mathematics, Vol. 223, Issue 2, 15 January 2009, pp. 790-800.<\/p>\n

K. Romanjek, L. Hutin, C. Le Royer, A. Pouydebasque, M. -A. Jaud, C. Tabone, E. Augendre, L. Sanchez, J.-M. Hartmann, H. Grampeix, V. Mazzocchi, S. Soliveres, R. Truche, L. Clavelier, P. Scheiblin, X. Garros, G. Reimbold, M. Vinet, F. Boulanger, S. Deleonibus,
\n“High performance 70 nm gate length germanium-on-insulator pMOSFET with high-k\/metal gate”,
\nSolid-State Electronics, Vol. 53, Issue 7, July 2009, pp. 723-729.<\/p>\n

M. Y. Yunus, M. Rusop,
\n“Effect of gate dielectric to the threshold voltage of 65 nm NMOS structure”,
\nAIP Conference Proceedings, Vol. 1136, 2009, pp. 570-574.<\/p>\n

Shadi A. Dayeh, Darija Susac, Karen L. Kavanagh, Edward T. Yu, Deli Wang,
\n“Structural and room-temperature transport properties of zinc blende and wurtzite inas nanowires”,
\nAdvanced Functional Materials, Vol. 19, No. 13, July 10 2009, pp. 2102-2108.<\/p>\n

Shadi A. Dayeh, Cesare Soci, Xin-Yu Bao, Deli Wang,
\n“Advances in the synthesis of InAs and GaAs nanowires for electronic applications”,
\nNano Today, Vol. 4, Issue 4, August 2009, pp. 347-358.<\/p>\n

Lianxi Jia, Minming Geng, Lei Zhang, Lin Yang, Ping Chen, Tong Wang, Yuliang Liu,
\n“Wavelength conversion based on degenerate-four-wave-mixing with continuous-wave pumping in silicon nanowire waveguide”,
\nOptics Communications, Vol. 282, Issue 8, 15 April 2009, pp. 1659-1663.<\/p>\n

S. Saurabh and M. Jagadesh Kumar,
\n“Impact of Strain on Drain Current and Threshold Voltage of Nanoscale Double Gate Tunnel Field Effect Transistor: Theoretical Investigation and Analysis”,
\nJapanese Journal of Applied Physics, No. 48 (2009), pp. 064503-1.<\/p>\n

Sang-Kwon Lee, Seung-Yong Lee, Konstantinos Rogdakis, Chan-Oh Jang, Dong-Joo Kim, Edwige Bano, Konstantinos Zekentes,
\n“Si nanowire p-FET with asymmetric source-drain I-V characteristics”,
\nSolid State Communications, Vol. 149, Issues 11-12, March 2009, pp. 461-463.<\/p>\n

M. Reyboz, P. Martin, T. Poiroux, O. Rozeau,
\n“Continuous model for independent double gate MOSFET”,
\nSolid-State Electronics, In Press, Corrected Proof, Available online 28 March 2009.<\/p>\n

T. Z. Mohamad, I. Ahmad, A. Zaharim,
\n“Optimum solution in fabricating 65 nm NMOS transistors using Taguchi method”,
\nAdvances on Applied Computer and Applied Computational Science. Proceedings of the 7th WSEAS International Conference on Applied Computer & Applied Computational Science (ACACOS ’08), pp. 451-6, 2008.<\/p>\n

S. Kolberg, H. B\u00f8rli, T.A. Fjeldly,
\n“Modeling, verification and comparison of short-channel double gate and gate-all-around MOSFETs”,
\nMathematics and Computers in Simulation, Vol. 79, Issue 4, 15 December 2008, pp. 1107-1115.<\/p>\n

Ismail Saad, Razali Ismail,
\n“Self-aligned vertical double-gate MOSFET (VDGM) with the oblique rotating ion implantation (ORI) method”,
\nMicroelectronics Journal, Vol. 39, Issue 12, December 2008, pp. 1538-1541.<\/p>\n

Vijay Sai Patnaik, Ankit Gheedia and M. Jagadesh Kumar,
\n“3D Simulation of Nanowire FETs using Quantum Models”<\/p>\n

Abhinav Kranti, G. Alastair Armstrong,
\n“How crucial is back gate misalignment\/oversize in double gate MOSFETs for ultra-low-voltage analog\/rf applications?”,
\nSolid-State Electronics, Vol. 52, Issue 12, December 2008, pp. 1895-1903.<\/p>\n

K. Modzelewski, R. Chintala, H. Moolamalla, S. Parke, D. Hackler,
\n“Design of a 32nm Independently-Double-Gated FlexFET SOI Transistor”,
\n17th Biennial University\/Government\/Industry Micro\/Nano Symposium, UGIM 2008. 13-16 July 2008, pp. 64-67.<\/p>\n

Qi Jianwen, Cheng Xiulan, Masayasu Tanjyo,
\n“Simulation on the effect of Halo implantation precision on the performance of 36NM NMOSFET device”,
\nSemiconductor Technology, ISTC 2008 – Proceedings of the 7th International Conference on Semiconductor Technology, PV 2008-1, 2008, pp. 58-63.<\/p>\n

Suzhen Luan, Hongxia Liu, Renxu Jia, Naiqiong Cai, Jin Wang, Qianwei Kuang,
\n“Analytical model of drain current for ultra-thin body and double-gate schottky source\/drain MOSFETs accounting for quantum effects”,
\nPan Tao Ti Hsueh Pao\/Chinese Journal of Semiconductors, Vol. 29, No. 5, May 2008, pp. 869-874.<\/p>\n

H\u00e5kon B\u00f8rli, Sigbj\u00f8rn Kolberg, Tor A. Fjeldly,
\n“Capacitance modeling of short-channel double-gate MOSFETs”,
\nSolid-State Electronics, Vol. 52, Issue 10, October 2008, pp. 1486-1490.<\/p>\n

Kathy Boucart, Adrian Mihai Ionescu,
\n“A new definition of threshold voltage in Tunnel FETs”,
\nSolid-State Electronics, Vol. 52, Issue 9, September 2008, pp. 1318-1323.<\/p>\n

Sang H. Lee, Geunbae Lim, Wonkyu Moon, Hyunjung Shin, Cheong-Wol Kim,
\n“V-shaped meta-oxide-semiconductor transistor probe with nano tip for surface electric properties”,
\nUltramicroscopy, Vol. 108, Issue 10, September 2008, pp. 1094-1100.<\/p>\n

Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta, R.S. Gupta,
\n“Intermodulation distortion and linearity performance assessment of 50-nm gate length L-DUMGAC MOSFET for RFIC design”,
\nSuperlattices and Microstructures, Vol. 44, Issue 2, August 2008, pp. 143-152.<\/p>\n

Luan Suzhen, Liu Hongxia, Jia Renxu, Cai Naiqiong, Wang Jin, Kuang Qianwei,
\n“An analytical model of drain current for ultra-thin body and double-gate Schottky source\/drain MOSFETs accounting for quantum effects”,
\nChinese Journal of Semiconductors, Vol. 29, n 5, p 869-74, May 2008.<\/p>\n

S. Kolberg, H. B\u00f8rli, and T. A. Fjeldly,
\n“Modeling, Verification and Comparison of Short-Channel Double Gate and Gate-All-Around MOSFETs”,
\nJ. Math. and Comp. in Simulation, in press.<\/p>\n

H. B\u00f8rli, S. Kolberg, and T. A. Fjeldly,
\n“Physics Based Current and Capacitance Model of Short-Channel Double Gate and Gate-All-Around MOSFETs”,
\ninvited, Proc. IEEE Int. Conf. on Nanoelectronics, March 24-27, 2008, Shanghai, China, pp. 844-849. IEEE ref. 978-1-4244-1573-1\/08.<\/p>\n

H. B\u00f8rli, S. Kolberg, T. Fjeldly, and B. I\u00f1guez,
\n“Current and Capacitance Modeling of Short-Channel DG MOSFETs”,
\nProc. 7th Int. IEEE Caribbean Conf. on Devices, Circuits and Systems (ICCDCS’08), Cancun, Mexico, April 28-30, 2008, paper no. 19. IEEE ref. 978-1-4244-1957-9\/08.<\/p>\n

H. B\u00f8rli, S. Kolberg, and T. A. Fjeldly,
\n“Capacitance modeling of Short-Channel DG and GAA MOSFETs”,
\ninvited paper, NSTI Nanotech 2008, Workshop on Compact Modeling, CRC Press, Boston, MA, June 1-5, 2008, vol. 3, pp. 745-749, 2008. ISBN: 978-1-4200-8505-1 (CD: ISBN 978-1-4200-8511-2).<\/p>\n

H. B\u00f8rli, K. Vinkenes, and T. A. Fjeldly,
\n“Physics based Capacitance Modeling of Short-Channel Double-Gate MOSFETs”,
\nPhysica Status Solidi (c), 1-4 (2008), in press. (DOI 10.1002\/pssc.200780124).<\/p>\n

S. Kolberg, H. B\u00f8rli, and T. A. Fjeldly,
\n“Compact Current Modeling of Short-Channel Multiple Gate MOSFETs”,
\nPhysica Status Solidi (c), 1-4 (2008), in press. (DOI 10.1002\/pssc.200880125).<\/p>\n

H. B\u00f8rli, S. Kolberg, and T. A. Fjeldly,
\n“Capacitance Modeling of Short-Channel Double-Gate MOSFETs”,
\nSolid State Electronics, Vol. 52, pp. 1486-1490, 2008.<\/p>\n

H. B\u00f8rli, S. Kolberg, T. A. Fjeldly, and B. I\u00f1guez,
\n“Precise Modeling Framework for Short-Channel Double-Gate and Gate-All-Around MOSFETs”
\nIEEE Trans. Electron Devices, vol. 55, no.10, pp. 2678-2686, 2008,<\/p>\n

T. A. Fjeldly and H. B\u00f8rli,
\n“2-D Modeling of Nanoscale Multigate MOSFETs”,
\ninvited, Proc. 9th Int Conf. on Solid-State and Integr.- Circ. Techn. (ICSICT’08), Beijing, China, Oct. 2008.<\/p>\n

Antonio Cerdeira, Benjamin Iniguez, Magali Estrada,
\n“Compact model for short channel symmetric doped double-gate MOSFETs”,
\nSolid-State Electronics, Vol. 52, Issue 7, Jul. 2008, pp. 1064-1070.<\/p>\n

Sona P. Kumar, Anju Agrawal, Rishu Chaujar, Mridula Gupta, R. S. Gupta,
\n“Analytical modeling and simulation of subthreshold behavior in nanoscale dual material gate AlGaN\/GaN HEMT”,
\nSuperlattices and Microstructures, Vol. 44, Issue 1, Jul. 2008, pp. 37-53.<\/p>\n

Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta, R. S. Gupta,
\n“Intermodulation distortion and linearity performance assessment of 50-nm gate length L-DUMGAC MOSFET for RFIC design”
\nSuperlattices and Microstructures, In Press, Corrected Proof, Available online 17 June 2008.<\/p>\n

V. Sverdlov, E. Ungersboeck, H. Kosina and S. Selberherr,
\n“Current transport models for nanoscale semiconductor devices”,
\nMaterials Science and Engineering: R: Reports, Vol. 58, Issue 6, 7 January 2008, pp. 228-270.<\/p>\n

K. Rogdakis, Seoung-Yong Lee, M. Bescond, Sang-Kwon Lee, E. Bano, K. Zekentes,
\n“3C-Silicon Carbide Nanowire FET: An Experimental and Theoretical Approach”,
\nElectron Devices, IEEE Transactions on Vol. 55, Issue 8, Aug. 2008 pp. 1970 – 1976.<\/p>\n

A. Bindal, S. Hamedi-Hagh,
\n“Silicon Nano-Wire Transistors and their Applications for the Future of VLSI: an Exploratory Design Study of a 16×16 SRAM”
\n(accepted by Journal of Nanoelectronics and Optoelectronics).<\/p>\n

A. Bindal, T. Ogura, S. Hamedi-Hagh,
\n“Silicon Nano-Wire Technology for the Use of Field Programmable Gate Array Structures”
\n(submitted to IEEE Transactions on Nanotechnology).<\/p>\n

Abhinav Kranti and G. Alastair Armstrong,
\n“Source\/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications”,
\nMicroelectronic Engineering, Vol. 84, Issue 12, December 2007, pp. 2775-2784.<\/p>\n

Chi-Woo Lee, Se-Re-Na Yun, Chong-Gun Yu, Jong-Tae Park and Jean-Pierre Colinge,
\n“Device design guidelines for nano-scale MuGFETs”,
\nSolid-State Electronics, Vol. 51, Issue 3, March 2007, pp. 505-510.<\/p>\n

A. Bindal, A. Naresh, P. Yuan, K. K. Nguyen, S. Hamedi-Hagh,
\n“The Design of Dual Work Function CMOS Transistors and Circuits Using Silicon Nano-Wire Technology”,
\nIEEE Trans. Nanotechnology, Vol. 6, No. 3, pp. 291-302, 2007.<\/p>\n

A. Bindal, S. Hamedi-Hagh,
\n“The Design of a New Spiking Neuron Using Silicon Nano-Wire Technology”,
\nNanotechnology (Institute of Physics), Vol. 18, 095201, 2007.<\/p>\n

A. Bindal, S. Hamedi-Hagh,
\n“Static NMOS Circuits Using Silicon Nano-Wire Technology for Crossbar Architectures”,
\nSemicond. Sci. Technol. (Institute of Physics), Vol. 22, pp. 54-64, 2007.<\/p>\n

A. Bindal, S. Hamedi-Hagh,
\n“An Exploratory Study on Power Efficent Silicon Nano-Wire Dynamic NMOSFET\/PMESFET Logic”,
\nIET (formerly IEE) Sci. Meas. Technol. Vol. 1, No. 2, pp. 121-130, 2007.<\/p>\n

A. Bindal, S. Hamedi-Hagh,
\n“A New Spiking Neuron Design Using Silicon Nano-Wire Technology”,
\nProc. of Nano Sci. and Technol. Inst. (NSTI), San Jose, California, 2007.<\/p>\n

Chin Hong Teoh, R. Ismail,
\n“Device Design Consideration for Nanoscale MOSFET Using Semiconductor TCAD Tools”,
\nIEEE International Conference on Semiconductor Electronics, 2006. ICSE ’06. Oct. 29 2006 – Dec. 1 2006, pp. 906 – 910.<\/p>\n

Jaehong Lee, Junsoo Kim, Juhwan Jung, Seungbum Hong, Byung-Gook Park, Jong Duk Lee, Hyungcheol Shin,
\n“A new resistive probe with higher resolution”,
\nIEEE Nanotechnology Materials and Devices Conference, 2006. NMDC 2006. Vol. 1, 22-25 Oct. 2006, pp. 114 – 115.<\/p>\n

C. Ravariu, A. Rusu, F. Udrea, F. Ravariu,
\n“Simulations results of some Diamond On Insulator nano-MISFETs”
\nDiamond and Related Materials. Vol. 15, No. 4-8, Apr. – Aug. 2006, pp. 777-782.<\/p>\n

A. Bindal, S. Hamedi-Hagh,
\n“The Impact of Silicon Nano-Wire Technology on the Design of Single Work Function CMOS Transistors and Circuits”,
\nNanotechnology (Institute of Physics), Vol. 17, ppp. 4340-4351, 2006.<\/p>\n

A. Bindal, S. Hamedi-Hagh,
\n“The Design and Analysis of Dynamic NMOSFET\/PMESFET Logic Using Silicon Nano-Wire Technology”,
\nSemicond. Sci. Technol. (Institute of Physics), Vol. 21, ppp. 1002-1012, 2006.<\/p>\n

A. Bindal, K. Aflatooni,
\n“The Design of a Silicon Wire DRAM Cell for Very Dense DRAM Architectures”,
\nProc. of Nano Sci. and Technol. Inst. (NSTI), Anaheim, California, 2005.<\/p>\n

A. K. Goel, H. Gopinathannair,
\n“Capacitance extraction for the nanoscale on-chip interconnects”,
\nIEEE International Conference on Semiconductor Electronics, 2004. ICSE 2004. 7-9 Dec. 2004 pp. 5.<\/p>\n

I. Pesic, A. Mutlu, N. Gunther, M. Rahman, J. Schulze, W. Hansch, I. Eisele,
\n“Single-electron-transistor behavior in deep sub-0.1”
\nDevice Research Conference – Conference Digest, DRC 2004, pp. 93-94.<\/p>\n

A. Ferron1<\/sup>, B. Cottle2<\/sup>, G. Curatola3<\/sup>, G. Fiori3<\/sup>, E. Guichard1<\/sup>,
\n“Schr\u00f6dinger Approach and Density Gradient Model for Quantum Effects Modeling”,
\n1 Silvaco Data Systems, 55 rue Blaise Pascal, 38330 Montbonnot Saint-Martin, France
\n2 Silvaco International, 2811 Mission Blvd. 6th Floor, Santa Clara, CA 95054, USA
\n3 University of Pisa, Via Diotisalvi 2, I-56122, Pisa, Italy<\/p>\n

A. Bindal, D. Parent, L. He, S. Kilic,
\n“A MOSFET Design Laboratory”,
\nInt. Conf. Eng. Edu., Gainesville, Florida, 2004.<\/p>\n

C. Kim, M. Li, A. Lowe, N. Venkataramaiah, K. Richmond, J. Kaysen, F. Cerrina,
\n“DNA microarrays: An imaging study”
\nJournal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, 2003, Vol. 21, Issue 6, pp. 2946-2950.<\/p>\n

G. M. Kim, A. Kovalgin, J. Holleman and et al.,
\n“Replication molds having nanometer-scale shape control fabricated by means of oxidation and etching”
\nJournal of Nanoscience and Nanotechnology, Vol. 2, Feb. 2002, pp. 55-59.<\/p>\n<\/div><\/section><\/div>

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