{"id":35792,"date":"2020-07-07T21:53:10","date_gmt":"2020-07-07T21:53:10","guid":{"rendered":"https:\/\/silvaco.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/model-extraction-flow-with-utmost-iv-for-vertically-stacked-nanosheets-using-the-leti-nsp-mode\/"},"modified":"2026-10-02T06:07:53","modified_gmt":"2026-10-02T13:07:53","slug":"model-extraction-flow-with-utmost-iv-for-vertically-stacked-nanosheets-using-the-leti-nsp-mode","status":"publish","type":"post","link":"https:\/\/silvaco.com\/zh-hans\/analog-custom-design-zh-hans\/modeling-zh-hans\/modeling-webinars-zh-hans\/model-extraction-flow-with-utmost-iv-for-vertically-stacked-nanosheets-using-the-leti-nsp-mode\/","title":{"rendered":"Model Extraction Flow with Utmost IV for Vertically Stacked Nanosheets Using the Leti-NSP Model"},"content":{"rendered":"<p><img loading=\"lazy\" width=\"1920\" height=\"201\" src=\"https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar.jpg\" class=\"cleaned-enfold-image\" alt=\"Banner Blue\" decoding=\"async\" loading=\"lazy\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar.jpg 1920w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-300x31.jpg 300w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-1030x108.jpg 1030w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-768x80.jpg 768w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-1536x161.jpg 1536w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-1500x157.jpg 1500w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-705x74.jpg 705w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-43x5.jpg 43w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-63x7.jpg 63w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-48x5.jpg 48w\" sizes=\"auto, (max-width: 1920px) 100vw, 1920px\" \/><\/p>\n<h1>Model Extraction Flow with Utmost IV for Vertically Stacked Nanosheets Using the Leti-NSP Model<\/h1>\n<p>Leti-NSP is an innovative model for advanced multi-gate MOSFETs. The model covers state-of-the art devices such as vertically stacked or vertical channel nanosheet\/nanowires and FinFETs. In this webinar we will present a parameter extraction methodology for Vertically Stacked Nanosheets, based on this model. The extraction flow has been implemented in the Silvaco Utmost IV modeling software. We will illustrate the extraction flow step by step, emphasizing the particularities of its implementation in Utmost IV. Both the Verilog-A version of the model as well as the built-in model implementation in the Silvaco SmartSpice circuit simulator will be covered.<\/p>\n<h4>What attendees will learn:<\/h4>\n<ul>\n<li>Extraction of SPICE Model parameters for Vertically Stacked Nanosheets using the Leti-NSP model<\/li>\n<li>Step-by-step illustration of the extraction flow implemented in Utmost IV<\/li>\n<li>Comparison between the Verilog-A and the built-in version of the Leti-NSP model<\/li>\n<\/ul>\n<h2>Presenter<\/h2>\n<p><img decoding=\"async\" class=\"wp-image-6449 size-full alignleft\" src=\"\/wp-content\/uploads\/2020\/03\/bogdan.jpg\" alt=\"\" width=\"100\" height=\"100\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/03\/bogdan.jpg 100w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/03\/bogdan-80x80.jpg 80w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/03\/bogdan-36x36.jpg 36w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/03\/bogdan-37x37.jpg 37w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/03\/bogdan-55x55.jpg 55w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/03\/bogdan-48x48.jpg 48w\" sizes=\"(max-width: 100px) 100vw, 100px\" \/>Dr. Bogdan Tudor is head of Silvaco\u2019s Device Characterization Group. He is responsible for all aspects of the Device Characterization Group\u2019s activities, including R&amp;D, field operations, and modeling services. He has 15+ year experience in EDA and SPICE modeling fields with extensive expertise in Device characterization, Compact Model development, MOSFET Aging Reliability Analysis, and Software development. Dr. Tudor holds a M.Sc. in Electrical Engineering and a Ph.D. in Microelectronics from the Polytechnic University in Bucharest, Romania.<\/p>\n<h3>WHO SHOULD ATTEND:<\/h3>\n<p>Engineers, management and academics, who are interested in SPICE modeling methodologies for advanced MOSFET devices, such as Nanosheets, in Verilog-A-based model extraction, and in SPICE model extraction and optimization, in general<\/p>\n<p><strong>When<\/strong>: July 30, 2020<br \/>\n<strong>Where<\/strong>: Online<br \/>\n<strong>Time<\/strong>: 10:00am-10:30am-(PDT)<br \/>\n<strong>Language<\/strong>: English<\/p>\n<div style=\"padding: 10px; background-color: #99ccff;\">\n<h1 align=\"center\">Register <!--to view On-Demand Webinar-->!<\/h1>\n<p><iframe style=\"border: 0;\" src=\"https:\/\/go.silvaco.com\/l\/145371\/2020-07-06\/2yfgxl\" width=\"100%\" height=\"590\" frameborder=\"0\"><\/iframe><\/p>\n<\/div>\n","protected":false},"excerpt":{"rendered":"<p><b>July 30, 2020 | 10:00 am \u2013 10:30 am (PDT)<\/b><br \/>\nThis webinar will provide a discussion of common methods used to secure an AMBA-based hardware and software system design.<\/p>\n","protected":false},"author":12,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"inline_featured_image":false,"footnotes":""},"categories":[7730],"tags":[],"class_list":["post-35792","post","type-post","status-publish","format-standard","hentry","category-modeling-webinars-zh-hans","entry"],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v28.7 (Yoast SEO v28.7) - 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