{"id":35544,"date":"2020-09-03T20:58:19","date_gmt":"2020-09-03T20:58:19","guid":{"rendered":"https:\/\/silvaco.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/choosing-the-right-ddr-memory-subsystem-for-your-next-soc\/"},"modified":"2021-09-22T13:50:58","modified_gmt":"2021-09-22T20:50:58","slug":"choosing-the-right-ddr-memory-subsystem-for-your-next-soc","status":"publish","type":"post","link":"https:\/\/silvaco.com\/zh-hans\/ip-zh-hans\/sipware-webinars-zh-hans\/choosing-the-right-ddr-memory-subsystem-for-your-next-soc\/","title":{"rendered":"Choosing the Right DDR Memory Subsystem for Your Next SOC!"},"content":{"rendered":"<div id='template_slider'  class='avia-fullwidth-slider main_color avia-shadow   avia-builder-el-0  el_before_av_section  avia-builder-el-first   container_wrap fullsize' style=' '  ><div   data-size='no scaling'  data-lightbox_size='large'  data-animation='slide'  data-conditional_play=''  data-ids='3925'  data-video_counter='0'  data-autoplay='false'  data-bg_slider='false'  data-slide_height=''  data-handle='av_slideshow_full'  data-interval='5'  data-class=' '  data-el_id=''  data-css_id=''  data-scroll_down=''  data-control_layout='av-control-default'  data-custom_markup=''  data-perma_caption=''  data-autoplay_stopper=''  data-image_attachment=''  data-min_height='110px'  data-lazy_loading='disabled'  data-src=''  data-position='top left'  data-repeat='no-repeat'  data-attach='scroll'  data-stretch=''  class='avia-slideshow avia-slideshow-1  av-control-default av-default-height-applied avia-slideshow-no scaling av_slideshow_full   avia-slide-slider '  itemprop=\"image\" itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/ImageObject\" ><ul class='avia-slideshow-inner ' style='padding-bottom: 10.46875%;' ><li  class=' av-single-slide slide-1 ' ><div data-rel='slideshow-1' class='avia-slide-wrap '   ><div class = \"caption_fullwidth av-slideshow-caption caption_bottom\"><div class = \"container caption_container\"><div class = \"slideshow_caption\"><div class = \"slideshow_inner_caption\"><div class = \"slideshow_align_caption\"><h2  style='font-size:50px; ' class='avia-caption-title   av-small-font-size-overwrite av-small-font-size-36 av-mini-font-size-overwrite av-mini-font-size-24'  itemprop=\"name\" >Webinars<\/h2><\/div><\/div><\/div><\/div><\/div><img decoding=\"async\" class=\"wp-image-18676 avia-img-lazy-loading-not-18676\"  src=\"https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar.jpg\" width=\"1920\" height=\"201\" title='Banner Blue' alt=''  itemprop=\"thumbnailUrl\"  style='min-height:110px; min-width:1051px; ' srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar.jpg 1920w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-300x31.jpg 300w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-1030x108.jpg 1030w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-768x80.jpg 768w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-1536x161.jpg 1536w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-1500x157.jpg 1500w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-705x74.jpg 705w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-43x5.jpg 43w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-63x7.jpg 63w, https:\/\/silvaco.com\/wp-content\/uploads\/2018\/12\/Webinar-48x5.jpg 48w\" sizes=\"(max-width: 1920px) 100vw, 1920px\" \/><\/div><\/li><\/ul><\/div><\/div>\n<div id='av_section_1'  class='avia-section main_color avia-section-small avia-no-border-styling  avia-bg-style-scroll  avia-builder-el-1  el_after_av_slideshow_full  avia-builder-el-last   container_wrap fullsize' style='background-color: #ffffff;  margin-top:0px; margin-bottom:0px; '  ><div class='container' ><div class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-35544'><div class='entry-content-wrapper clearfix'>\n<div class='flex_column_table av-equal-height-column-flextable -flextable' style='margin-top:20px; margin-bottom:0px; '><div class=\"flex_column av_three_fourth  flex_column_table_cell av-equal-height-column av-align-top first  avia-builder-el-2  el_before_av_one_fourth  avia-builder-el-first  \" style='padding:0px 0px 0px 0px ; border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/BlogPosting\" itemprop=\"blogPost\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1>Choosing the Right DDR Memory Subsystem for Your Next SoC!<\/h1>\n<p>As computational requirements continue to grow and memory systems are operating at even higher frequencies, the demand for high-performance memory subsystems that are more dense, consume less power, and occupy smaller silicon continues to grow rapidly across key application segments such as high-performance computing platforms, 5G, Automotive, and IoT applications.<\/p>\n<p>In this webinar, we will introduce Samsung Foundry PHY IP offerings with its unique technology, OpenEdges\u2019s multi-protocol controller, and Silvaco\u2019s subsystem IP. Attendees will learn how to achieve plug-and-play solutions for DDR memory subsystem in new SoC designs. Both technology features and complementary services to help design efficient memory subsystems will be included in the presentation.<\/p>\n<\/div><\/section><br \/>\n<div  style='background:#c7e1e5;color:#595959;border-color:#e0e0e0;' class='av_promobox  avia-button-yes   avia-builder-el-4  el_after_av_textblock  el_before_av_hr  mfp-hide'><div class='avia-promocontent'><\/p>\n<h3>To view our webinar register to view content.<\/h3>\n<p>\n<\/div><div  class='avia-button-wrap avia-button-right ' ><a href='\/dynamicweb\/jsp\/downloads\/DownloadDocStepsAction.do?req=silen-download&amp;nm=Machine_Learning_in_the_EDA_Specific_Domain.mp4&amp;prefixname=video'  class='avia-button  avia-color-grey   avia-icon_select-no avia-size-medium avia-position-right '   ><span class='avia_iconbox_title' >Register to View Archive<\/span><\/a><\/div><\/div><br \/>\n<div   class='hr hr-default   avia-builder-el-5  el_after_av_promobox  el_before_av_textblock '><span class='hr-inner ' ><span class='hr-inner-style'><\/span><\/span><\/div><br \/>\n<section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/BlogPosting\" itemprop=\"blogPost\" ><div class='avia_textblock mfp-hide '   itemprop=\"text\" ><h2>Presenter<\/h2>\n<\/div><\/section><br \/>\n<section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/BlogPosting\" itemprop=\"blogPost\" ><div class='avia_textblock  '   itemprop=\"text\" ><p><img loading=\"lazy\" decoding=\"async\" class=\"alignleft wp-image-13245 size-thumbnail\" src=\"\/wp-content\/uploads\/2020\/09\/Kwanyeob-80x80.jpg\" alt=\"Kwanyeob Chae\" width=\"80\" height=\"80\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/09\/Kwanyeob-80x80.jpg 80w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/09\/Kwanyeob-36x36.jpg 36w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/09\/Kwanyeob-37x37.jpg 37w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/09\/Kwanyeob-55x55.jpg 55w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/09\/Kwanyeob-48x48.jpg 48w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/09\/Kwanyeob.jpg 100w\" sizes=\"(max-width: 80px) 100vw, 80px\" \/><\/p>\n<p>Kwanyeob Chae is a Principal Engineer at Samsung Foundry and responsible for DDR PHY design in IP development team. He is engaged in the development of digital circuits and design methodologies for high speed memory interface. His research interests include design methodology, physical implementation, high speed digital PHY architecture, self-adaptive circuits, low-power circuits, and variation-tolerant design. Kwanyeob Chae received his B.S. and M.S. degrees in electronics engineering from Korea University, Seoul, Korea. He received his Ph.D. degree in electrical and computer engineering from Georgia Institute of Technology, Atlanta.<\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-13204 size-thumbnail alignleft\" src=\"\/wp-content\/uploads\/2020\/09\/seanLee-80x80.jpg\" alt=\"Sean Lee\" width=\"80\" height=\"80\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/09\/seanLee-80x80.jpg 80w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/09\/seanLee-36x36.jpg 36w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/09\/seanLee-37x37.jpg 37w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/09\/seanLee-55x55.jpg 55w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/09\/seanLee-48x48.jpg 48w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/09\/seanLee.jpg 100w\" sizes=\"(max-width: 80px) 100vw, 80px\" \/>Sean Lee is CEO of Openedges Technology, Inc. and responsible for managing strategic growth of the company through technological leadership. He has more than 20 years of IP and SoC design experiences including numerous generations of Exynos mobile AP for Galaxy Smartphones. His background includes CPU architecture, memory subsystem IP design, and mobile AP SoC design, and he holds several patents on memory subsystem architecture. Sean holds B.S. and M.S. degree in Electrical Engineering and Computer Science from Seoul National University of South Korea.<\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-11200 size-thumbnail alignleft\" src=\"\/wp-content\/uploads\/2020\/07\/ashish-80x80.jpg\" alt=\"Ashish Shrotriya\" width=\"80\" height=\"80\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/07\/ashish-80x80.jpg 80w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/07\/ashish-36x36.jpg 36w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/07\/ashish-37x37.jpg 37w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/07\/ashish-55x55.jpg 55w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/07\/ashish-48x48.jpg 48w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/07\/ashish.jpg 100w\" sizes=\"(max-width: 80px) 100vw, 80px\" \/>Ashish Shrotriya is Director of Worldwide Foundry and IP Business Development at Silvaco. Prior to Silvaco, Ashish has held senior strategic marketing and program management roles at leading semiconductor and IP companies including Honeywell, Applied Materials, Efficient Solar Power Systems, TSMC, and Virage Logic. Ashish is the author of five patents and holds an MBA from Cornell University and an MS in electrical engineering from Michigan Technological University.<\/p>\n<\/div><\/section><br \/>\n<div   class='hr hr-default   avia-builder-el-8  el_after_av_textblock  el_before_av_textblock '><span class='hr-inner ' ><span class='hr-inner-style'><\/span><\/span><\/div><br \/>\n<section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/BlogPosting\" itemprop=\"blogPost\" ><div class='avia_textblock  '   itemprop=\"text\" ><h3>WHO SHOULD ATTEND:<\/h3>\n<\/div><\/section><br \/>\n<section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/BlogPosting\" itemprop=\"blogPost\" ><div class='avia_textblock  '   itemprop=\"text\" ><div class=\"flex_column av_three_fourth flex_column_table_cell av-equal-height-column av-align-top first avia-builder-el-2 el_before_av_one_fourth avia-builder-el-first \">\n<section class=\"av_textblock_section \">\n<div class=\"avia_textblock \">\n<div class=\"col-md-7\">\n<div>\n<p>Engineers, manager, and executives looking to design SoCs for HPC, data center, AI\/ML, high-speed networking, 5G, and IoT applications.<\/p>\n<\/div>\n<\/div>\n<\/div>\n<\/section>\n<\/div>\n<\/div><\/section><\/p><\/div><div class='av-flex-placeholder'><\/div><div class=\"flex_column av_one_fourth  flex_column_table_cell av-equal-height-column av-align-top   avia-builder-el-11  el_after_av_three_fourth  avia-builder-el-last  \" style='padding:0px 0px 0px 0px ; border-radius:0px; '><p><section class=\"av_textblock_section \"  id=\"date\"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/BlogPosting\" itemprop=\"blogPost\" ><div class='avia_textblock  '   itemprop=\"text\" ><p><strong>When<\/strong>: October 13, 2020<br \/>\n<strong>Where<\/strong>: Online<br \/>\n<strong>Time<\/strong>: 10:00am-10:30am &#8211; (PST)<br \/>\n<strong>Language<\/strong>: English<\/p>\n<\/div><\/section><br \/>\n<div   class='hr hr-default   avia-builder-el-13  el_after_av_textblock  el_before_av_codeblock '><span class='hr-inner ' ><span class='hr-inner-style'><\/span><\/span><\/div><br \/>\n<br \/>\n<div  class='avia-button-wrap avia-button-center  avia-builder-el-15  el_after_av_codeblock  el_before_av_hr ' ><a href='\/dynamicweb\/jsp\/downloads\/DownloadDocStepsAction.do?req=silen-download&amp;nm=Choosing_the_Right_DDR_Memory_Subsystem.mp4&amp;prefixname=video'  class='avia-button  avia-color-grey   avia-icon_select-no avia-size-small avia-position-center '   ><span class='avia_iconbox_title' >Register to View Archive<\/span><\/a><\/div><br \/>\n<div   class='hr hr-default   avia-builder-el-16  el_after_av_button  avia-builder-el-last '><span class='hr-inner ' ><span class='hr-inner-style'><\/span><\/span><\/div><\/p><\/div><\/div><!--close column table wrapper. Autoclose: 1 -->\n","protected":false},"excerpt":{"rendered":"<p><b>October 13, 2020 | 10:00 am \u2013 10:30 am (PST)<\/b><br \/>\nAs computation requirements continue to build and memory systems are operating at ever higher frequencies, high-performance memory subsystems that consume minimal power consumption and small silicon area are a necessary requirement.<\/p>\n","protected":false},"author":3,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[7726],"tags":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v24.0 (Yoast SEO v24.0) - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Choosing the Right DDR Memory Subsystem for Your Next SOC! - Silvaco<\/title>\n<meta name=\"description\" content=\"As computation requirements continue to build and memory systems are operating at ever higher frequencies, high-performance memory subsystems\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/silvaco.com\/zh-hans\/ip-zh-hans\/sipware-webinars-zh-hans\/choosing-the-right-ddr-memory-subsystem-for-your-next-soc\/\" \/>\n<meta property=\"og:locale\" content=\"zh_CN\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Choosing the Right DDR Memory Subsystem for Your Next SOC!\" \/>\n<meta property=\"og:description\" content=\"As computation requirements continue to build and memory systems are operating at ever higher frequencies, high-performance memory subsystems\" \/>\n<meta property=\"og:url\" content=\"https:\/\/silvaco.com\/zh-hans\/ip-zh-hans\/sipware-webinars-zh-hans\/choosing-the-right-ddr-memory-subsystem-for-your-next-soc\/\" \/>\n<meta property=\"og:site_name\" content=\"Silvaco\" \/>\n<meta property=\"article:publisher\" content=\"https:\/\/www.facebook.com\/SilvacoSoftware\/\" \/>\n<meta property=\"article:published_time\" content=\"2020-09-03T20:58:19+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2021-09-22T20:50:58+00:00\" \/>\n<meta name=\"author\" content=\"Erick Castellon\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:creator\" content=\"@SilvacoSoftware\" \/>\n<meta name=\"twitter:site\" content=\"@SilvacoSoftware\" \/>\n<meta name=\"twitter:label1\" content=\"\u4f5c\u8005\" \/>\n\t<meta name=\"twitter:data1\" content=\"Erick Castellon\" \/>\n\t<meta name=\"twitter:label2\" content=\"\u9884\u8ba1\u9605\u8bfb\u65f6\u95f4\" \/>\n\t<meta name=\"twitter:data2\" content=\"8 \u5206\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"WebPage\",\"@id\":\"https:\/\/silvaco.com\/zh-hans\/ip-zh-hans\/sipware-webinars-zh-hans\/choosing-the-right-ddr-memory-subsystem-for-your-next-soc\/\",\"url\":\"https:\/\/silvaco.com\/zh-hans\/ip-zh-hans\/sipware-webinars-zh-hans\/choosing-the-right-ddr-memory-subsystem-for-your-next-soc\/\",\"name\":\"Choosing the Right DDR Memory Subsystem for Your Next SOC! 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