{"id":35486,"date":"2021-01-13T15:22:38","date_gmt":"2021-01-13T23:22:38","guid":{"rendered":"https:\/\/silvaco.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/how-to-simulate-semiconductor-materials-stress-and-deformation-with-silvaco-victory-tcad-solution\/"},"modified":"2026-10-02T07:15:51","modified_gmt":"2026-10-02T14:15:51","slug":"how-to-simulate-semiconductor-materials-stress-and-deformation-with-silvaco-victory-tcad-solution","status":"publish","type":"post","link":"https:\/\/silvaco.com\/zh-hans\/tcad-zh-hans\/tcad-webinars-zh-hans\/how-to-simulate-semiconductor-materials-stress-and-deformation-with-silvaco-victory-tcad-solution\/","title":{"rendered":"How to Simulate Semiconductor Materials Stress and Deformation with Silvaco Victory TCAD Solution"},"content":{"rendered":"

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How to Simulate Semiconductor Materials Stress and Deformation with Silvaco Victory TCAD Solution<\/h1>\n

Semiconductor devices are fabricated with many process steps such as etch, deposition, and thermal processes. Each process step changes the dynamics of stress profile; hence it is important to keep track of stress history step by step. Silvaco Victory TCAD solution for semiconductor stress is tightly integrated with process simulation flow and therefore offers important advantages over conventional standalone stress solvers.<\/p>\n

In this webinar we will cover the capabilities and usage of Victory TCAD Process<\/a> simulator and explain how materials and simulation parameters can be set, including boundary conditions, which solvers are supported and how to set up different types of simulation.<\/p>\n

We will also present several case studies related to stress problems which are observed in semiconductor manufacturing. These include FinFET bending during STI fill process, local material layer bending during etch process, back-end metal line bending due to thermal process. Finally, we will discuss the backend metal stress simulation during wire bonding process. This example shows the potential usage of the tool beyond conventional stress simulation leading into design rule check capability.<\/p>\n

Presenter<\/h2>\n

\"\"Dr. Jin Cho is Principal Application Engineer at Silvaco, based in Santa Clara, USA. Prior to joining Silvaco in 2018, he was with GLOBALFOUNDRIES\/AMD for 15 years where he held the position of process\/device manager of 14\/10nm logic technology development and managed TCAD group for future device technology research. Jin holds a Ph. D. from Stanford University.<\/p>\n

\"Dr.Dr. Artem Babayan is Senior Software Engineer at Silvaco, based in St Ives, Cambridgeshire, UK. He is responsible for the development of Victory Process core simulation engine. Artem has been with Silvaco since 2006. Dr. Babayan holds PhD in Applied Mathematics from the Rostov State University, Russia.\u00a0<\/strong><\/p>\n

WHO SHOULD ATTEND:<\/h3>\n

Engineers and management who are interested in simulating impact of stress as part of process simulation.\u00a0<\/strong><\/p>\n

When<\/strong>: March 18, 2021
\nWhere<\/strong>: Online
\nTime<\/strong>: 10:00am-10:30am-(PST)
\nLanguage<\/strong>: English<\/p>\n

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Register!<\/h1>\n