{"id":35392,"date":"2021-07-27T11:18:18","date_gmt":"2021-07-27T18:18:18","guid":{"rendered":"https:\/\/silvaco.com\/%e6%9c%aa%e5%88%86%e7%b1%bb\/webinars-silvaco-smartspice-2021-top-10-new-features-in-the-baseline-release\/"},"modified":"2026-10-02T06:30:24","modified_gmt":"2026-10-02T13:30:24","slug":"webinars-silvaco-smartspice-2021-top-10-new-features-in-the-baseline-release","status":"publish","type":"post","link":"https:\/\/silvaco.com\/zh-hans\/analog-custom-design-zh-hans\/spice-zh-hans\/spice-webinars-zh-hans\/webinars-silvaco-smartspice-2021-top-10-new-features-in-the-baseline-release\/","title":{"rendered":"Silvaco SmartSpice 2021 – Top 10 New Features in the Baseline Release"},"content":{"rendered":"

\"Banner<\/p>\n

Silvaco SmartSpice 2021 – Top 10 New Features in the Baseline Release<\/h1>\n

\"Opt-img-comb\"Silvaco\u2019s SmartSpice 2021 Baseline Release has just been released. In this webinar, we present the top 10 new features and improvements enabled by the SmartSpice team during this past year, which are focused on the following aspects:<\/p>\n

    \n
  1. Performance and capacity improvements: Up to 4x speedup and 9x memory reduction<\/li>\n
  2. Support for RHEL\/CentOS 8: A key enabler for those migrating away from RHEL\/CentOS 6<\/li>\n
  3. New Graphical User Interface (GUI) technology: Faster and more stable experience<\/li>\n
  4. Improvements on SmartSpice RF: Completely revised periodic steady-state and phase noise flows<\/li>\n
  5. Improvements on SmartSpice Pro: A variety of enhancements for a better user experience<\/li>\n
  6. Improved Spectre\u00ae compatibility mode: Key enablers for simulations using the Spectre language<\/li>\n
  7. Improvements on SmartSpice Server: Cross-platform simulation is now available<\/li>\n
  8. Improved Back Annotation flow: Extended support to improve robustness<\/li>\n
  9. Improved Parallel .ALTER flow: Control the number of threads of child processes<\/li>\n
  10. New External Sampling feature: Set yourself the values for statistical parameters when running Monte Carlo simulations.<\/li>\n<\/ol>\n

    What You Will Learn<\/h3>\n
      \n
    • Develop a greater understanding of new developments in Silvaco<\/li>\n
    • Improve setup and efficiency of simulations<\/li>\n<\/ul>\n

      Presenter<\/h2>\n

      \"JodyM_photo\"Dr. Jody Matos is a Ph.D. Computer Scientist who is passionate about research and development of software and hardware designs. Currently, he is Silvaco’s Director of Circuit Simulation, where he has been managing leading-edge R&D and business-related projects for EDA tools. His current tasks are mainly related to circuit simulation and analyses on analog, digital and mixed-signal IC designs. Dr. Matos joined Silvaco in 2018 as part of the Nangate acquisition, where he researched and developed EDA tools for layout automation and standard cell library characterization.
      \nDr. Matos received a Ph.D. degree in computer science from the Federal University do Rio Grande do Sul (UFRGS), Brazil, and a M.S. degree in microelectronics from the same institution. He has co-authored 30+ research papers and patent applications that mix knowledge of both computer science and microelectronics. Dr. Matos has also served on technical committees of several international conferences in the fields of design automation.<\/p>\n

      WHO SHOULD ATTEND:<\/h3>\n

      IP, Analog Circuit, CAD and SoC design engineers, product managers and engineering management in the circuit simulation field, and students new to circuit simulation.<\/p>\n

      When<\/strong>: August 19, 2021
      \nWhere<\/strong>: Online
      \nTime<\/strong>: 10:00am-10:30am-(PDT)
      \nLanguage<\/strong>: English<\/p>\n

      \n

      Register!<\/h1>\n