{"id":72190,"date":"2026-09-30T09:03:25","date_gmt":"2026-09-30T16:03:25","guid":{"rendered":"https:\/\/silvaco.com\/%e5%85%ac%e5%8f%b8\/%e6%96%b0%e9%97%bb\/"},"modified":"2026-10-07T07:52:30","modified_gmt":"2026-10-07T14:52:30","slug":"%e6%96%b0%e9%97%bb","status":"publish","type":"page","link":"https:\/\/silvaco.com\/zh-hans\/%e5%85%ac%e5%8f%b8\/%e6%96%b0%e9%97%bb\/","title":{"rendered":"\u65b0\u95fb"},"content":{"rendered":"\t\t
\n\t\t\t\t
\n\t\t\t\t\t
\n\t\t
\n\t\t\t\t
\n\t\t\t\t\t

\u9996\u9875 > \u516c\u53f8 > \u65b0\u95fb<\/h3>\t\t\t\t<\/div>\n\t\t\t\t
\n\t\t\t\t\t

Silvaco \u65b0\u95fb\u4e0e\u65b0\u95fb\u7a3f<\/h1>\t\t\t\t<\/div>\n\t\t\t\t
\n\t\t\t\t\t\t\t\t\t

\u81ea 2019 \u5e74 1 \u6708\u4ee5\u6765\uff0cSilvaco \u5df2\u53d1\u5e03 77 \u7bc7\u65b0\u95fb\u7a3f\uff0c\u5185\u5bb9\u6db5\u76d6\u5ba2\u6237\u3001\u5408\u4f5c\u4f19\u4f34\u3001\u4ea7\u54c1\u548c\u516c\u53f8\u52a8\u6001\u3002\u6700\u8fd1\u4e00\u7bc7\u4e8e 2026 \u5e74 8 \u6708 18 \u65e5\u53d1\u5e03\uff0c\u5ba3\u5e03\u4e0e Dassault Syst\u00e8mes \u5efa\u7acb\u5408\u4f5c\u4f19\u4f34\u5173\u7cfb\u3002<\/p>\n\t\t\t\t\t\t\t\t<\/div>\n\t\t

\n\t\t\t\t
\n\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t<\/path><\/svg>\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\u901a\u8fc7\u7535\u5b50\u90ae\u4ef6\u83b7\u53d6 Silvaco \u65b0\u95fb<\/span>\n\t\t\t\t\t<\/span>\n\t\t\t\t\t<\/a>\n\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t
\n\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t<\/path><\/svg>\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\u6d4f\u89c8\u65b0\u95fb\u7a3f<\/span>\n\t\t\t\t\t<\/span>\n\t\t\t\t\t<\/a>\n\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t
\n\t\t\t\t\t
\n\t\t\t\t
\n\t\t\t\t\t

Silvaco \u6700\u65b0\u65b0\u95fb<\/h2>\t\t\t\t<\/div>\n\t\t\t\t
\n\t\t\t\t\t\t\t\t\t

\u5ba2\u6237\u91c7\u7528\u3001\u5408\u4f5c\u4f19\u4f34\u5173\u7cfb\u3001\u4ea7\u54c1\u53d1\u5e03\u548c\u516c\u53f8\u516c\u544a\uff0c\u65e0\u8bba\u60a8\u5173\u6ce8\u7684\u662f AI
\u9a71\u52a8\u5236\u9020\u8fd8\u662f AI \u9a71\u52a8\u8bbe\u8ba1\u4e1a\u52a1\uff0c\u90fd\u53ef\u5728\u6b64\u83b7\u53d6\u76f8\u5173\u4fe1\u606f\u3002<\/p>\n

\u5b63\u5ea6\u4e1a\u7ee9\u548c SEC \u7533\u62a5\u6587\u4ef6\u540c\u6837\u5c5e\u4e8e Silvaco \u65b0\u95fb\u3002\u8fd9\u4e9b\u5185\u5bb9\u53ef\u5728
investors.silvaco.com<\/a> \u67e5\u770b\uff0c\u5176\u4e2d 2026 \u5e74\u7b2c\u4e8c\u5b63\u5ea6\u8d22\u52a1\u4e1a\u7ee9\u4e8e 2026 \u5e74 8 \u6708 6 \u65e5\u53d1\u5e03\u3002<\/p>\n\t\t\t\t\t\t\t\t<\/div>\n\t\t

\n\t\t\t\t
\n\t\t\t\t\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t<\/path><\/svg>\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\u524d\u5f80\u6295\u8d44\u8005\u65b0\u95fb<\/span>\n\t\t\t\t\t<\/span>\n\t\t\t\t\t<\/a>\n\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t
\n\t\t\t\t\t

\u5a92\u4f53\u54a8\u8be2\uff1apress@silvaco.com<\/a><\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
\n\t\t\t\t
\n\t\t\t\t\t
869 \u7bc7\u6587\u7ae0<\/div><\/div>
October 2, 2026<\/div>
\u672a\u5206\u7c7b<\/div><\/div>

GaN and SiC Power Semiconductor Markets Exceed $1B in 2021<\/a><\/h3>
Market energized by demand from hybrid & electric vehicles, power supplies and photovoltaic inverters. By Richard Eden, Omdia Research The emerging market\u2026<\/div><\/div><\/article>
June 30, 2026<\/div>
Simulation Standard<\/div><\/div>

1200 V\u5782\u76f4\u578b\u6c2e\u5316\u9553FinFET\u6676\u4f53\u7ba1\u7684TCAD\u51fb\u7a7f\u4eff\u771f<\/a><\/h3>
\u672c\u6587\u5229\u7528Silvaco Victory\u5de5\u5177\u5957\u4ef6\uff0c\u5bf9\u4e00\u98971200 V\u5782\u76f4\u578b\u6c2e\u5316\u9553\uff08GaN\uff09FinFET\u6676\u4f53\u7ba1\u8fdb\u884c\u4e86TCAD\u5de5\u827a\u4eff\u771f\u3001\u7f51\u683c\u751f\u6210\u53ca\u5668\u4ef6\u4eff\u771f\u3002<\/div><\/div><\/article>
June 3, 2026<\/div>
Webinars<\/div><\/div>

\u5229\u7528FTCO\u2122\u548c\u6570\u5b57\u5b6a\u751f\u6280\u672f\u52a0\u901f\u9762\u5411\u5236\u9020\u7684\u7845\u5149\u96c6\u6210\u7535\u8def\u4eff\u771f<\/a><\/h3>
TCAD Webinars<\/span><\/div>
2026\u5e747\u67089\u65e5 10\uff1a00AM CST<\/div><\/div><\/article>
May 29, 2026<\/div>
\u672a\u5206\u7c7b<\/div><\/div>

Silvaco at DAC 2026<\/a><\/h3>
Silvaco\u9080\u60a8\u76f8\u7ea6DAC 2026 2026\u5e747\u670826\u65e5-29\u65e5 \u5730\u70b9\uff1a\u957f\u6ee9\u4f1a\u8bae\u4e2d\u5fc3 | \u5c55\u4f4d\u53f7\uff1a1155 Silvaco\u8bda\u9080\u60a8\u8385\u4e34DAC\u5c55\u4f1a\uff0c\u4e0e\u6211\u4eec\u4e00\u540c\u89c1\u8bc1\u534a\u5bfc\u4f53\u8bbe\u8ba1\u9886\u57df\u7684\u521b\u65b0\u5b9e\u8df5\u3002\u6b22\u8fce\u5149\u4e34\u6211\u4eec\u7684\u5c55\u4f4d\uff0c\u4e86\u89e3\u6211\u4eec\u5728AI\u9a71\u52a8\u8bbe\u8ba1\u3001\u5efa\u6a21\u53caIP\u89e3\u51b3\u65b9\u6848\u65b9\u9762\u7684\u6700\u65b0\u8fdb\u5c55\u4e0e\u7a81\u7834\u3002 \u7279\u8272\u6280\u672f Utmost \u2014 AI \u9a71\u52a8\u7684 SPICE \u6a21\u578b\u63d0\u53d6\u4e0e\u7279\u5f81\u5316\u5de5\u5177 \u5feb\u901f\u751f\u6210\u7cbe\u786e\u3001\u53ef\u76f4\u63a5\u7528\u4e8e\u8bbe\u8ba1\u7684\u7d27\u51d1\u6a21\u578b\uff0c\u5927\u5e45\u7f29\u77ed\u5f00\u53d1\u5468\u671f\u3002 Utmost\u80fd\u5c06\u5de5\u827a\u4e0e\u5668\u4ef6\u6570\u636e\u9ad8\u6548\u8f6c\u5165\u53ef\u9760\u7684SPICE\u6a21\u578b\uff0c\u786e\u4fdd\u4eff\u771f\u4e0e\u5b9e\u9645\u7845\u7247\u7279\u6027\u9ad8\u5ea6\u4e00\u81f4\uff0c\u540c\u65f6\u663e\u8457\u51cf\u5c11\u4eba\u5de5\u8c03\u53c2\u3001\u964d\u4f4e\u6a21\u578b\u4e0d\u786e\u5b9a\u6027\uff0c\u5e76\u907f\u514d\u6210\u672c\u9ad8\u6602\u7684\u91cd\u590d\u6d41\u7247\u3002 Jivaro \/ Viso \u2014 AI \u9a71\u52a8\u7684\u5bc4\u751f\u53c2\u6570\u4e0e\u6a21\u62df\u5206\u6790\u89e3\u51b3\u65b9\u6848\u2026<\/div><\/div><\/article>
May 19, 2026<\/div>
News<\/div><\/div>

Silvaco Announces Immediate Availability of Mixel MIPI C-PHY\/D-PHY Combo IP on TSMC N2P Process<\/a><\/h3>
May 19, 2026<\/div><\/div><\/article>
May 15, 2026<\/div>
Webinars<\/div><\/div>

\u9762\u5411 GAA-NS-FET \u5168\u5668\u4ef6\u5c3a\u5bf8\u8bbe\u8ba1\u63a2\u7d22\u4e0e\u4f18\u5316\u7684\u5feb\u901f\u96c6\u6210\u91cf\u5b50\u8f93\u8fd0\u89e3\u51b3\u65b9\u6848<\/a><\/h3>
TCAD Webinars<\/span><\/div>
\u89c6\u9891\u56de\u653e\u5df2\u4e0a\u7ebf<\/div><\/div><\/article>
May 8, 2026<\/div>
News<\/div><\/div>

Silvaco Reports First Quarter 2026 Financial Results<\/a><\/h3>
May 7, 2026<\/div><\/div><\/article>
April 27, 2026<\/div>
Simulation Standard<\/div><\/div>

\u5229\u7528AI\u9a71\u52a8\u7684FTCO\u52a0\u901f\u4e0b\u4e00\u4ee3\u529f\u7387\u6280\u672f\u53d1\u5c55<\/a><\/h3>
\u6211\u4eec\u6700\u65b0\u4e00\u671f\u7684 Simulation Standard \u63a2\u8ba8\u4e86Silvaco\u7684AI\u9a71\u52a8\u578b\u5236\u9020\u6280\u672f\u534f\u540c\u4f18\u5316 (FTCO\u2122) \u5e73\u53f0\u901a\u8fc7\u7ed3\u5408\u89c4\u6a21\u5316\u4eff\u771f\u3001\u667a\u80fd\u5b9e\u9a8c\u8bbe\u8ba1\u548c\u673a\u5668\u5b66\u4e60\u4ee3\u7406\u6a21\u578b\uff0c\u5982\u4f55\u53d8\u9769\u529f\u7387\u5668\u4ef6\u5f00\u53d1\u5de5\u4f5c\u6d41\u7a0b\uff0c\u5e76\u4ee5pGaN HEMTs\u3001\u5782\u76f4\u578bGaN\u548cSiC DMOS\u6280\u672f\u4e3a\u5b9e\u4f8b\u8fdb\u884c\u6f14\u793a\u8bb2\u89e3\u3002<\/div><\/div><\/article>
April 20, 2026<\/div>
News<\/div><\/div>

Silvaco Partners with ITRI to Support MCU Development and Startup Innovation<\/a><\/h3>
April 20, 2026<\/div><\/div><\/article>
April 9, 2026<\/div>
Webinars<\/div><\/div>

\u52a0\u901f\u4e0b\u4e00\u4ee3\u529f\u7387\u6280\u672f<\/a><\/h3>
TCAD Webinars<\/span><\/div>
\u89c6\u9891\u56de\u653e\u5df2\u4e0a\u7ebf<\/div><\/div><\/article>
March 30, 2026<\/div>
News<\/div><\/div>

Silvaco Announces Strategic Partnership with APEC to Advance Silicon Carbide Power Device Development<\/a><\/h3>
March 30, 2026<\/div><\/div><\/article>
March 19, 2026<\/div>
Simulation Standard<\/div><\/div>

\u53e0\u5c42\u6709\u673a\u53d1\u5149\u4e8c\u6781\u7ba1\u7684\u6709\u673a\u8f93\u8fd0\u6a21\u578b<\/a><\/h3>
\u4e0b\u4e00\u4ee3\u663e\u793a\u6280\u672f\u6b63\u91c7\u7528\u53e0\u5c42\u6709\u673a\u53d1\u5149\u4e8c\u6781\u7ba1\u62d3\u6251\u7ed3\u6784\u6765\u63d0\u5347\u9762\u677f\u6027\u80fd\u3002<\/div><\/div><\/article>
March 12, 2026<\/div>
News<\/div><\/div>

Silvaco Reports Fourth Quarter and Full-Year 2025 Financial Results<\/a><\/h3>
March 12, 2026<\/div><\/div><\/article>
March 10, 2026<\/div>
News<\/div><\/div>

Silvaco Announces Immediate Availability of Production Ready Mixel MIPI PHY IP, Strengthening its Comprehensive Silicon IP Offering<\/a><\/h3>
March 10, 2026<\/div><\/div><\/article>
March 5, 2026<\/div>
Webinars<\/div><\/div>

\u6784\u5efa\u66f4\u4f18\u3001\u66f4\u5feb\u7684\u5148\u8fdb\u903b\u8f91\u5668\u4ef6\uff1a\u4ece\u5de5\u827a\u5230\u5668\u4ef6\u4eff\u771f\u3001\u6821\u51c6\u53ca FTCO\u2122 \u5de5\u4f5c\u6d41<\/a><\/h3>
TCAD Webinars<\/span><\/div>
\u89c6\u9891\u56de\u653e\u5df2\u4e0a\u7ebf<\/div><\/div><\/article>
February 3, 2026<\/div>
\u672a\u5206\u7c7b<\/div><\/div>

SURGE Virtual Event Japan 2026<\/a><\/h3>
SURGE Virtual Event Japan 2026 Archive Now Available Silvaco SURGE unites the semiconductor development and design community to explore how Silvaco\u2019s simulation\u2026<\/div><\/div><\/article>
January 21, 2026<\/div>
Simulation Standard<\/div><\/div>

\u8d4b\u80fd\u4e0b\u4e00\u4ee3\u9ad8\u538b\u529f\u7387\u5668\u4ef6\uff1a\u4ece\u4eff\u771f\u5230\u7cfb\u7edf\u7684\u6c27\u5316\u9553\u6c9f\u69fd\u8096\u7279\u57fa\u4e8c\u6781\u7ba1<\/a><\/h3>
\u03b2-Ga\u2082O\u2083\u6709\u671b\u5f7b\u5e95\u53d8\u9769\u9ad8\u538b\u529f\u7387\u8f6c\u6362\u9886\u57df\uff0c\u5176\u8d85\u4f4e\u635f\u8017\u548c\u9ad8\u4e34\u754c\u7535\u573a\u7279\u6027\u4f7f\u4e4b\u6210\u4e3a\u4e0b\u4e00\u4ee3\u529f\u7387\u5668\u4ef6\u7684\u7406\u60f3\u9009\u62e9[1]\uff0c\u80fd\u591f\u4e3aAI\u6570\u636e\u4e2d\u5fc3\u4f9b\u7535\u3001\u53ef\u518d\u751f\u80fd\u6e90\u7cfb\u7edf[2]\u3001\u9ad8\u538b\u65ad\u8def\u5668\u548c\u9759\u7535\u653e\u7535\u4fdd\u62a4[3]\u63d0\u4f9b1\u20136 kV\u30010.5\u20130.8 kA\u8303\u56f4\u5185\u7684\u4e09\u76f8\u9ad8\u538b\u76f4\u6d41\u7684AC\/DC\u548cDC\/AC\u8f6c\u6362\u65b9\u6848\u3002<\/div><\/div><\/article>
January 21, 2026<\/div>
\u672a\u5206\u7c7b<\/div><\/div>

SURGE Virtual Event North America 2026<\/a><\/h3>
SURGE Virtual Event North America 2026 Archive Now Available Silvaco SURGE unites the semiconductor development and design community to explore how Silvaco\u2019s\u2026<\/div><\/div><\/article>
January 13, 2026<\/div>
\u672a\u5206\u7c7b<\/div><\/div>

SURGE Virtual Event EMEA 2026<\/a><\/h3>
SURGE Virtual Event EMEA 2026 Archive Now Available Silvaco SURGE unites the semiconductor development and design community to explore how Silvaco\u2019s simulation\u2026<\/div><\/div><\/article>
December 18, 2025<\/div>
Simulation Standard<\/div><\/div>

Victory TCAD 2025 \u8f6f\u4ef6\u7248\u672c\u53d1\u5e03<\/a><\/h3>
\u51ed\u501f\u56db\u5341\u4f59\u5e74\u7684\u6df1\u539a\u79ef\u6dc0\uff0cSilvaco \u53d1\u5e03\u7684 Victory TCAD\u2122 2025 \u7248\u672c\uff0c\u518d\u6b21\u5f15\u9886 TCAD \u9886\u57df\u7684\u521b\u65b0\u6d6a\u6f6e\u3002\u8be5\u7248\u672c\u5728\u4eff\u771f\u5f15\u64ce\u3001\u6c42\u89e3\u5668\u6027\u80fd\u3001\u7269\u7406\u6a21\u578b\u4ee5\u53ca\u9762\u5411\u5927\u89c4\u6a21 3D \u5e94\u7528\u7684\u591a\u7269\u7406\u573a\u5de5\u4f5c\u6d41\u7a0b\u65b9\u9762\u5747\u5b9e\u73b0\u4e86\u91cd\u5927\u63d0\u5347\u3002<\/div><\/div><\/article>
November 20, 2025<\/div>
News<\/div><\/div>

Mixel MIPI IP Integrated into Automotive Radar Processors Supporting Safety-critical Applications<\/a><\/h3>
November 20, 2025<\/div><\/div><\/article>
November 18, 2025<\/div>
Simulation Standard<\/div><\/div>

\u57fa\u4e8e\u7269\u7406\u7684\u6570\u5b57\u5b6a\u751f\uff0c\u52a0\u901f\u9762\u5411AI\u5de5\u5382\u7684800V\u9ad8\u538b\u76f4\u6d41\u5782\u76f4\u578bGaN\u529f\u7387\u5668\u4ef6\u5f00\u53d1<\/a><\/h3>
\u6211\u4eec\u5c06\u8ba8\u8bba\u57fa\u4e8e\u7269\u7406\u7684\u6570\u5b57\u5b6a\u751f\uff0c\u52a0\u901f\u9762\u5411AI\u5de5\u5382\u7684800V\u9ad8\u538b\u76f4\u6d41\u5782\u76f4\u578bGaN\u529f\u7387\u5668\u4ef6\u5f00\u53d1<\/div><\/div><\/article>
November 18, 2025<\/div>
POST<\/div><\/div>

\u52a0\u901f\u9ad8\u6027\u80fd\u50cf\u7d20\u5f00\u53d1\uff1a\u57fa\u4e8eTCAD\u7684\u6570\u5b57\u5b6a\u751f\u6280\u672f\u8d4b\u80fd\u65b0\u4e00\u4ee3CIS<\/a><\/h3>
TCAD Webinars<\/span><\/div>
\u89c6\u9891\u56de\u653e\u5df2\u4e0a\u7ebf<\/div><\/div><\/article>
November 12, 2025<\/div>
News<\/div><\/div>

Silvaco Reports Third Quarter 2025 Financial Results<\/a><\/h3>
November 12, 2025\u00a0<\/div><\/div><\/article>
November 10, 2025<\/div>
News<\/div><\/div>

Silvaco Reaches Settlement Resolving Prior Litigation with Former Nangate Shareholders<\/a><\/h3>
November 10, 2025\u00a0<\/div><\/div><\/article>
October 27, 2025<\/div>
News<\/div><\/div>

Vicor Adopts Silvaco\u2019s Victory TCAD\u2122 3D Simulation Solution for Accurate Power Device Modeling and Simulation<\/a><\/h3>
October 28, 2025<\/div><\/div><\/article>
October 23, 2025<\/div>
Webinars<\/div><\/div>

\uff08\u4e2d\u6587\u7814\u8ba8\u4f1a\uff09\u5229\u7528TCAD\u4e0e\u57fa\u4e8e\u7269\u7406\u7684\u6570\u5b57\u5b6a\u751f\u6280\u672f\u52a0\u901fGaN\u5668\u4ef6\u8bbe\u8ba1<\/a><\/h3>
TCAD Webinars<\/span><\/div>
\u89c6\u9891\u56de\u653e\u5df2\u4e0a\u7ebf<\/div><\/div><\/article>
September 21, 2025<\/div>
Simulation Standard<\/div><\/div>

\u529f\u7387MOSFET\u52a8\u6001\u6d4b\u8bd5<\/a><\/h3>
\u672c\u6587\u6f14\u793a\u4e86\u5982\u4f55\u5e94\u7528Silvaco TCAD\u5de5\u5177\u5957\u4ef6\uff0c\u5bf9\u5e73\u9762\u578b\u78b3\u5316\u7845MOSFET\uff08DMOS\uff09\u5b9e\u73b0\u4ece\u5de5\u827a\u5236\u7a0b\u5230\u7535\u8def\u5206\u6790\u7684\u5168\u6d41\u7a0b\u4eff\u771f\u3002<\/div><\/div><\/article>
September 19, 2025<\/div>
News<\/div><\/div>

Analog Power Conversion LLC adopts Silvaco\u2019s Design Technology Co-Optimization Flow for Next Generation Silicon and Silicon Carbide Power Devices<\/a><\/h3>
September 16, 2025<\/div><\/div><\/article>
September 4, 2025<\/div>
Webinars<\/div><\/div>

\u5229\u7528TCAD\u4e0e\u57fa\u4e8e\u7269\u7406\u7684\u6570\u5b57\u5b6a\u751f\u6280\u672f\u52a0\u901f\u6c2e\u5316\u9553\uff08GaN\uff09\u5668\u4ef6\u8bbe\u8ba1<\/a><\/h3>
TCAD Webinars<\/span><\/div>
\u89c6\u9891\u56de\u653e\u5df2\u4e0a\u7ebf<\/div><\/div><\/article>
September 4, 2025<\/div>
News<\/div><\/div>

Silvaco Names Chris Zegarelli as Chief Financial Officer<\/a><\/h3>
September 4, 2025<\/div><\/div><\/article>
August 22, 2025<\/div>
News<\/div><\/div>

Silvaco Announces CEO Transition<\/a><\/h3>
August 21, 2025<\/div><\/div><\/article>
August 15, 2025<\/div>
Simulation Standard<\/div><\/div>

\u963b\u6297\u573a\u4e0e\u4f4e\u4fe1\u53f7\u566a\u58f0<\/a><\/h3>
\u4f4e\u4fe1\u53f7\u7535\u6c14\u566a\u58f0\u4e0d\u53ef\u907f\u514d\uff0c\u5176\u6210\u56e0\u5728\u4e8e\u5668\u4ef6\u5185\u90e8\u8fc7\u7a0b\u7684\u968f\u673a\u6ce2\u52a8\uff0c\u4f8b\u5982\u70ed\u6ce2\u52a8\u5bfc\u81f4\u7684\u8f7d\u6d41\u5b50\u5bc6\u5ea6\u5fae\u89c2\u53d8\u5316\uff0c\u4ee5\u53ca\u4ea7\u751f-\u590d\u5408\u901f\u7387\u7684\u7edf\u8ba1\u6ce2\u52a8\u3002 \u6b64\u7c7b\u566a\u58f0\u53ef\u80fd\u5e72\u6270\u7535\u8def\u9884\u671f\u884c\u4e3a\uff0c\u56e0\u6b64\u5efa\u6a21\u5668\u4ef6\u4ea7\u751f\u7684\u566a\u58f0\u81f3\u5173\u91cd\u8981\u3002\u4e86\u89e3\u566a\u58f0\u5728\u5668\u4ef6\u4e2d\u7684\u5177\u4f53\u4ea7\u751f\u4f4d\u7f6e\u4ea6\u5177\u6709\u91cd\u8981\u610f\u4e49\uff0c\u8fd9\u6709\u52a9\u4e8e\u8bbe\u8ba1\u4f4e\u566a\u58f0\u5668\u4ef6\u3002Victory Device\u91c7\u7528\u963b\u6297\u573a\u6cd5\u8fdb\u884c\u566a\u58f0\u8ba1\u7b97\u3002<\/div><\/div><\/article>
August 15, 2025<\/div>
Simulation Standard<\/div><\/div>

\u5728 Victory Process \u7684\u8499\u7279\u5361\u6d1b\u79bb\u5b50\u6ce8\u5165\u4e2d\u4f7f\u7528 Trajectory Replication<\/a><\/h3>
Victory Process\u4e2d\u7684\u8499\u7279\u5361\u6d1b\u79bb\u5b50\u6ce8\u5165\u662f\u56fa\u4f53\u7ed3\u6784\u7684\u5de5\u827a\u4eff\u771f\u4e2d\u5b9e\u73b0\u7269\u7406\u4e0a\u7cbe\u786e\u7684\u6d53\u5ea6\u5206\u5e03\u7684\u91cd\u8981\u5de5\u5177\u3002\u8be5\u8499\u7279\u5361\u6d1b\u7b97\u6cd5\u901a\u8fc7\u6a21\u62df\u7c92\u5b50\u4ece\u6ce8\u5165\u7a97\u53e3\u8fdb\u5165\u7528\u6237\u6240\u5b9a\u4e49\u7684\u7ed3\u6784\u540e\u7684\u8fd0\u52a8\u8def\u5f84\u8fdb\u884c\u5efa\u6a21\u5de5\u4f5c\u3002\u7c92\u5b50\u5728\u7ed3\u6784\u5185\u79fb\u52a8\u65f6\uff0c\u901a\u8fc7\u4e0e\u6750\u6599\u76f8\u4e92\u4f5c\u7528\u4e0d\u65ad\u635f\u5931\u80fd\u91cf\uff0c\u76f4\u81f3\u505c\u6b62\u8fd0\u52a8\u6216\u53d1\u751f\u80cc\u6563\u5c04\u3002\u8981\u83b7\u5f97\u7edf\u8ba1\u6ce2\u52a8\u8f83\u5c0f\u4e14\u6d53\u5ea6\u5206\u5e03\u8fde\u7eed\uff08\u5e73\u6ed1\uff09\u7684\u7ed3\u679c\uff0c\u901a\u5e38\u9700\u8981\u8017\u8d39\u5927\u91cf\u8ba1\u7b97\u65f6\u95f4\u3002Trajectory Replication\u7684\u76ee\u6807\u662f\u901a\u8fc7\u5c06\u7c92\u5b50\u5728\u7ed3\u6784\u67d0\u533a\u57df\u7684\u8fd0\u52a8\u8def\u5f84\u590d\u5236\u5230\u5176\u4ed6\u533a\u57df\uff0c\u5728\u4fdd\u6301\u6d53\u5ea6\u5206\u5e03\u5e73\u6ed1\u5ea6\u7684\u540c\u65f6\u6709\u6548\u51cf\u5c11\u603b\u4f53\u8ba1\u7b97\u65f6\u95f4\u3002\u4e3a\u5b9e\u73b0\u7269\u7406\u4e0a\u7cbe\u786e\u7684\u7ed3\u679c\uff0c\u590d\u5236\u64cd\u4f5c\u5fc5\u987b\u6ee1\u8db3\u660e\u786e\u5b9a\u4e49\u7684\u6761\u4ef6\uff0c\u672c\u6587\u5c06\u5bf9\u76f8\u5173\u6761\u4ef6\u8fdb\u884c\u9610\u8ff0\u3002\u5728\u5177\u4f53\u4ecb\u7ecd\u590d\u73b0\u6d41\u7a0b\u7684\u7ec6\u8282\u4e4b\u524d\uff0c\u6211\u4eec\u5c06\u5148\u8ba8\u8bba\u8499\u7279\u5361\u6d1b\u79bb\u5b50\u6ce8\u5165\u7a0b\u5e8f\u4e2d\u7684\u82e5\u5e72\u91cd\u8981\u6982\u5ff5\u3002<\/div><\/div><\/article>
August 13, 2025<\/div>
News<\/div><\/div>

Silvaco\u2019s CEO, Babak Taheri, to Attend the Jefferies\u2019 Semis, IT Hardware & Comm Tech Summit in Chicago<\/a><\/h3>
August 13, 2025<\/div><\/div><\/article>
August 11, 2025<\/div>
News<\/div><\/div>

Silvaco To Present at the Rosenblatt 5th Annual Technology Summit<\/a><\/h3>
August 11, 2025<\/div><\/div><\/article>
August 6, 2025<\/div>
News<\/div><\/div>

Silvaco Reports Second Quarter 2025 Financial Results<\/a><\/h3>
August 6, 2025<\/div><\/div><\/article>
August 4, 2025<\/div>
News<\/div><\/div>

Silvaco Completes Acquisition of Mixel Group, Inc. a Provider of Low-Power, High-Performance Mixed-Signal Connectivity IP Solutions<\/a><\/h3>
August 4, 2025<\/div><\/div><\/article>
July 29, 2025<\/div>
News<\/div><\/div>

Silvaco Strengthens Leadership Team with Three Industry Veterans to Drive Innovation and Growth<\/a><\/h3>
July 24, 2025<\/div><\/div><\/article>
July 24, 2025<\/div>
News<\/div><\/div>

Silvaco Announces Date of Second Quarter 2025 Financial Results Conference Call<\/a><\/h3>
July 23, 2025<\/div><\/div><\/article>
July 14, 2025<\/div>
Webinars<\/div><\/div>

\u5982\u4f55\u4f7f\u7528Victory Atomistic\u8fdb\u884c\u73af\u6805\u5668\u4ef6\u4eff\u771f<\/a><\/h3>
TCAD Webinars<\/span><\/div>
\u89c6\u9891\u56de\u653e\u5df2\u4e0a\u7ebf<\/div><\/div><\/article>
July 2, 2025<\/div>
News<\/div><\/div>

Wavetek Deploys Silvaco\u2019s Victory TCAD\u2122 to Drive Innovation in GaN-Based Connectivity Solutions<\/a><\/h3>
July 1, 2025<\/div><\/div><\/article>
June 27, 2025<\/div>
News<\/div><\/div>

Silvaco to Host a Tech Talk on the Diffusion of Innovation<\/a><\/h3>
June 17, 2025<\/div><\/div><\/article>
June 24, 2025<\/div>
News<\/div><\/div>

Silvaco and Fraunhofer ISIT Collaborate to Advance Next-Generation GaN Device Technology using Silvaco\u2019s DTCO Flow<\/a><\/h3>
June 24, 2025<\/div><\/div><\/article>
June 3, 2025<\/div>
News<\/div><\/div>

Silvaco To Present at the Rosenblatt 5th Annual Technology Summit<\/a><\/h3>
May 28, 2025<\/div><\/div><\/article>
May 13, 2025<\/div>
News<\/div><\/div>

Alps Alpine Adopts Silvaco\u2019s Jivaro Pro to Accelerate SPICE Post-Layout Simulation<\/a><\/h3>
May 13, 2025<\/div><\/div><\/article>
May 7, 2025<\/div>
News<\/div><\/div>

Silvaco Reports First Quarter 2025 Financial Results<\/a><\/h3>
May 7, 2025<\/div><\/div><\/article>
May 6, 2025<\/div>
News<\/div><\/div>

Excelliance MOS\u00a0Adopts Silvaco DTCO Flow for the Development of Next-Gen Silicon Carbide Devices<\/a><\/h3>
May 6, 2025<\/div><\/div><\/article>
May 1, 2025<\/div>
News<\/div><\/div>

Silvaco Partners with Kyung Hee University\u2019s Professor Jin Jang on AI-Powered Fab Technology Co-Optimization for Next Generation Display Technologies<\/a><\/h3>
May 1, 2025<\/div><\/div><\/article>
April 29, 2025<\/div>
News<\/div><\/div>

Silvaco Expands Product Offerings in Photonics and Wafer-Scale Plasma Modeling for AI Applications with Acquisition of Tech-X Corporation<\/a><\/h3>
April 29, 2025<\/div><\/div><\/article>
April 11, 2025<\/div>
POST<\/div><\/div>

\u5982\u4f55\u4f7f\u7528Silvaco TCAD\u8fdb\u884c\u7845\u57fa\u5668\u4ef63D\u4eff\u771f<\/a><\/h3>
TCAD Webinars<\/span><\/div>
\u89c6\u9891\u56de\u653e\u5df2\u4e0a\u7ebf<\/div><\/div><\/article>
April 1, 2025<\/div>
Custom Webinars<\/div><\/div>

\u5982\u4f55\u4f7f\u7528 Viso \u68c0\u67e5\u3001\u5206\u6790\u548c\u89e3\u51b3\u590d\u6742\u7684\u5bc4\u751f\u95ee\u9898<\/a><\/h3>
\u89c6\u9891\u56de\u653e\u5df2\u4e0a\u7ebf<\/div><\/div><\/article>
April 1, 2025<\/div>
News<\/div><\/div>

ProMOS Adopts Silvaco Victory TCAD Solution for the Development of Next-Gen Silicon Photonics Devices<\/a><\/h3>
April 2, 2025<\/div><\/div><\/article>
March 25, 2025<\/div>
News<\/div><\/div>

Faraday Technology Selects Silvaco FlexCAN IP for Advanced Automotive ASIC Design<\/a><\/h3>
March 25, 2025<\/div><\/div><\/article>
March 24, 2025<\/div>
News<\/div><\/div>

Silvaco Announces Departure of Chief Financial Officer<\/a><\/h3>
March 21, 2025<\/div><\/div><\/article>
March 6, 2025<\/div>
News<\/div><\/div>

Silvaco Reports Fourth Quarter and Full Year 2024 Financial Results<\/a><\/h3>
March 5, 2025<\/div><\/div><\/article>
February 26, 2025<\/div>
Simulation Standard<\/div><\/div>

A New CMOS Simulation Template: Addressing Advanced Diffusion and Annealing Effects<\/a><\/h3>
As the scaling of CMOS devices continues, the accuracy requirements for simulating ion implantation and diffusion processes have become increasingly stringent.<\/div><\/div><\/article>
February 4, 2025<\/div>
POST<\/div><\/div>

Victory Process\u4e2dCMOS\u6280\u672f\u7684\u5efa\u6a21\u6846\u67b6<\/a><\/h3>
TCAD Webinars<\/span><\/div>
\u89c6\u9891\u56de\u653e\u5df2\u4e0a\u7ebf<\/div><\/div><\/article>
January 28, 2025<\/div>
Simulation Standard<\/div><\/div>

\u865a\u62df\u91cf\u6d4b\u65b0\u5de5\u5177\u7b80\u4ecb\uff1aVictory Extract<\/a><\/h3>
Victory Extract\u662fSilvaco\u57282024\u57fa\u51c6\u7248\u672c\u8f6f\u4ef6\u4e2d\u63a8\u51fa\u7684\u4e00\u4e2a\u65b0\u5de5\u5177\uff0c\u5b83\u7edf\u4e00\u4e86\u51e0\u6b3e\u8f6f\u4ef6\u4e2d\u7684\u63d0\u53d6\u5de5\u5177\uff08DeckBuild\u7684extract\u3001Victory Process\u7684extract3d\u548cVictory Mesh\u7684extract3d\uff09\uff0c\u5e76\u5f15\u5165\u4e86\u4e00\u4e9b\u65b0\u7684\u91cf\u6d4b\u529f\u80fd\u3002<\/div><\/div><\/article>
January 14, 2025<\/div>
News<\/div><\/div>

Silvaco Announces Preliminary Unaudited Fourth Quarter and Full-Year 2024 Results Ahead of Participation at Needham\u2019s 27th Annual Growth Conference<\/a><\/h3>
January 14, 2025<\/div><\/div><\/article>
December 20, 2024<\/div>
News<\/div><\/div>

Micon Global and Silvaco Announce New Partnership<\/a><\/h3>
December 20, 2024<\/div><\/div><\/article>
December 19, 2024<\/div>
News<\/div><\/div>

Silvaco Announces that The Ninth Circuit affirmed the dismissal of all claims against Silvaco brought by Aldini AG<\/a><\/h3>
December 19, 2024<\/div><\/div><\/article>
December 4, 2024<\/div>
News<\/div><\/div>

Silvaco Joins SMART USA Institute to Propel Digital Twin Innovations Under CHIPS Manufacturing USA Program<\/a><\/h3>
December 4, 2024<\/div><\/div><\/article>
November 28, 2024<\/div>
POST<\/div><\/div>

\u5982\u4f55\u5229\u7528 Victory Analytics \u548c\u673a\u5668\u5b66\u4e60\u6821\u51c6 TCAD \u6570\u636e<\/a><\/h3>
TCAD Webinars<\/span><\/div>
\u89c6\u9891\u56de\u653e\u5df2\u4e0a\u7ebf<\/div><\/div><\/article>
November 13, 2024<\/div>
News<\/div><\/div>

Silvaco Reports Third Quarter 2024 Financial Results<\/a><\/h3>
November 12, 2024<\/div><\/div><\/article>
October 25, 2024<\/div>
News<\/div><\/div>

Silvaco Inc. Achieves ISO 9001 Certification for Comprehensive Suite of TCAD, EDA, and IP Products<\/a><\/h3>
October 25, 2024<\/div><\/div><\/article>
October 16, 2024<\/div>
News<\/div><\/div>

Silvaco Announces Preliminary Unaudited Revenue for Q3 and Updates Full Year 2024<\/a><\/h3>
October 15, 2024<\/div><\/div><\/article>
September 30, 2024<\/div>
News<\/div><\/div>

Silvaco Appoints Candace Jackson as Senior Vice President, General Counsel, and Corporate Secretary<\/a><\/h3>
September 30, 2024<\/div><\/div><\/article>
September 23, 2024<\/div>
Simulation Standard<\/div><\/div>

\u57fa\u4e8e\u53cc\u8109\u51b2\u6cd5\u7684IGBT\u5f00\u5173\u4eff\u771f<\/a><\/h3>
\u6211\u4eec\u5c06\u5728\u672c\u671f\u4e3a\u60a8\u4ecb\u7ecd\u4e00\u79cd\u57fa\u4e8eDPT\u7684\u4eff\u771f\u65b9\u6cd5\uff0c\u6765\u7814\u7a76IGBT\u5668\u4ef6\u7684\u77ac\u6001\u5f00\u5173\u7279\u6027\u3002\u6587\u7ae0\u8fd8\u63d0\u4f9b\u4e86\u4e00\u5957\u4f7f\u7528Silvaco TCAD\u4eff\u771f\u5de5\u5177\u8bc4\u4f30\u529f\u7387\u5668\u4ef6\u5f00\u5173\u7279\u7684\u6807\u51c6\u6a21\u677f\u548c\u65b9\u6cd5\uff0c\u6240\u7528\u7684\u4eff\u771f\u4ee3\u7801\u53ef\u53c2\u80032024\u57fa\u51c6\u7248\u672c\u7684\u793a\u4f8bSilicon_Power_ex17\u3002<\/div><\/div><\/article>
September 23, 2024<\/div>
News<\/div><\/div>

Silvaco Expands its Victory TCAD and Digital Twin Modeling Platform to Planar CMOS, FinFET and Advanced CMOS Technologies<\/a><\/h3>
September 24, 2024<\/div><\/div><\/article>
September 18, 2024<\/div>
News<\/div><\/div>

Silvaco Announces Expected Addition to Three US Russell Indexes<\/a><\/h3>
September 16, 2024<\/div><\/div><\/article>
September 9, 2024<\/div>
POST<\/div><\/div>

\u5982\u4f55\u4ee5\u539f\u5b50\u7ea7\u7cbe\u5ea6\u4eff\u771f\u4e8c\u7ef4TMD\u6c9f\u9053FET\uff1f<\/a><\/h3>
TCAD Webinars<\/span><\/div>
\u89c6\u9891\u56de\u653e\u5df2\u4e0a\u7ebf<\/div><\/div><\/article>
August 28, 2024<\/div>
Simulation Standard<\/div><\/div>

2024 TCAD\u57fa\u51c6\u7248\u672c\u8f6f\u4ef6\u53d1\u5e03<\/a><\/h3>
\u7b2c\u4e00\u90e8\u5206\uff1aVictory Process\u2014\u20142024\u57fa\u51c6\u7248\u672c\u4e2d\u7684\u65b0\u529f\u80fd \u7b2c\u4e8c\u90e8\u5206\uff1aVictory Device\u2014\u20142024\u57fa\u51c6\u7248\u672c\u4e2d\u7684\u65b0\u529f\u80fd \u7b2c\u4e09\u90e8\u5206\uff1aVictory DoE\u2014\u20142024\u57fa\u51c6\u7248\u672c\u4e2d\u7684\u65b0\u529f\u80fd<\/div><\/div><\/article>
August 7, 2024<\/div>
Webinars<\/div><\/div>

\u7f8e\u5149\u79d1\u6280\uff1a\u5982\u4f55\u5229\u7528Silvaco\u7684FTCO<sup>TM<\/sup>\u5e73\u53f0\u8fdb\u884c\u5b58\u50a8\u6280\u672f\u7684\u5f00\u53d1\u548c\u5236\u9020<\/a><\/h3>
TCAD Webinars<\/span><\/div>
\u89c6\u9891\u56de\u653e\u5df2\u4e0a\u7ebf<\/div><\/div><\/article>
August 7, 2024<\/div>
News<\/div><\/div>

Silvaco Reports Second Quarter 2024 Financial Results<\/a><\/h3>
August 7, 2024<\/div><\/div><\/article>
July 5, 2024<\/div>
Webinars<\/div><\/div>

\u5c06\u4eba\u5de5\u667a\u80fd\u5e94\u7528\u4e8eFTCO<sup>TM<\/sup><\/a><\/h3>
TCAD Webinars<\/span><\/div>
2024\u5e747\u670825\u65e5 FTCO\u57fa\u4e8e\u5b9e\u9645\u751f\u4ea7\u5de5\u827a\u4e2d\u7684\u7269\u7406\u548c\u5316\u5b66\u673a\u5236\uff0c\u5229\u7528\u4eba\u5de5\u667a\u80fd\uff08AI\uff09\u548c\u673a\u5668\u5b66\u4e60\uff08ML\uff09\u751f\u6210\u7cbe\u786e\u7684TCAD\u6570\u5b57\u6a21\u578b\uff08\u6570\u5b57\u5b6a\u751f\uff09\u3002\u5bf9\u4e8e\u8fd9\u79cd\u6570\u5b57\u5b6a\u751f\u6a21\u578b\uff0c\u53ef\u4ee5\u91c7\u7528DoE\u65b9\u6cd5\u8fdb\u884c\u6d4b\u8bd5\u548c\u5206\u6790\uff0c\u800c\u65e0\u9700\u771f\u5b9e\u6d41\u7247\uff0c\u4ece\u800c\u5927\u5927\u8282\u7701\u4e86\u5236\u9020\u76f8\u5173\u7684\u65f6\u95f4\u548c\u8d39\u7528\u3002<\/div><\/div><\/article>
June 21, 2024<\/div>
News<\/div><\/div>

Silvaco Reports First Quarter 2024 Financial Results<\/a><\/h3>
June 20, 2024<\/div><\/div><\/article>
June 11, 2024<\/div>
News<\/div><\/div>

Silvaco Announces Initiatives to Enhance Workforce Development in Semiconductor Industry<\/a><\/h3>
TCAD News<\/span><\/div>
June 12, 2024<\/div><\/div><\/article>
June 10, 2024<\/div>
Simulation Standard<\/div><\/div>

How Can I Re-Use Individual Monte-Carlo 3D Implant Profiles?<\/a><\/h3>
It is often the case that a design of experiments (DOE) is required to optimize the performance of a particular device. \u00a0Sometimes\u2026<\/div><\/div><\/article>
May 23, 2024<\/div>
Simulation Standard<\/div><\/div>

Comparison of Models for Fluorine Effect on Dopant Diffusion in CMOS Processes<\/a><\/h3>
Recently a new diffusion model was introduced to Victory Process: the CMOS model. This model aims at taking on the challenges brought\u2026<\/div><\/div><\/article>
May 8, 2024<\/div>
Custom News<\/div><\/div>

Silvaco Announces Pricing of Initial Public Offering<\/a><\/h3>
Library News<\/span>SPICE News<\/span>TCAD News<\/span>Variation News<\/span><\/div>
May 8, 2024<\/div><\/div><\/article>
April 29, 2024<\/div>
Custom News<\/div><\/div>

Silvaco Announces Launch of Initial Public Offering<\/a><\/h3>
Modeling News<\/span>SIPware News<\/span>SPICE News<\/span>TCAD News<\/span>Variation News<\/span><\/div>
April 30, 2024<\/div><\/div><\/article>
April 16, 2024<\/div>
Custom News<\/div><\/div>

Silvaco Announces Expanded Partnership with Micron Technology<\/a><\/h3>
Foundation IP News<\/span>Library News<\/span>Modeling News<\/span>Parasitics+Netlist News<\/span>SIPware News<\/span>SPICE News<\/span>TCAD News<\/span>Variation News<\/span><\/div>
April 16, 2024<\/div><\/div><\/article>
April 1, 2024<\/div>
Simulation Standard<\/div><\/div>

Setting up the Wafer Orientation: Applications to Ion Implantation<\/a><\/h3>
Properly setting the wafer orientation in Victory Process (VP) is critical for various processes such as ion implantation, etching, and deposition. For\u2026<\/div><\/div><\/article>
March 11, 2024<\/div>
Simulation Standard<\/div><\/div>

Optoelectronic Component Design for Photonic Integrated Circuits<\/a><\/h3>
Photonic integrated circuits (PICs) are a key enabling technology for a broad range of current and next-generation products. Combining semiconductor materials and\u2026<\/div><\/div><\/article>
February 27, 2024<\/div>
POST<\/div><\/div>

\u610f\u6cd5\u534a\u5bfc\u4f53\uff1a\u5982\u4f55\u4f7f\u7528Silvaco TCAD\u7814\u7a76\u8868\u9762\u7f3a\u9677\u70b9\u5bf9SiC\u5668\u4ef6\u77ed\u8def\u73b0\u8c61\u7684\u5f71\u54cd<\/a><\/h3>
TCAD Webinars<\/span><\/div>
2024\u5e743\u670828\u65e5 \u5728\u6253\u5f00\u548c\u5173\u95edSiC\u5668\u4ef6\u65f6\uff0c\u5668\u4ef6\u5bb9\u6613\u51fa\u73b0\u5f02\u5e38\u8fc7\u8f7d\uff0c\u56e0\u6b64\u5728\u4e00\u4e9b\u5e94\u7528\u4e2d\u5bf9\u5668\u4ef6\u201c\u9c81\u68d2\u6027\u201d\u6709\u8981\u6c42\uff0c\u4f8b\u5982\u9700\u8fdb\u884c\u77ed\u8def\u6d4b\u8bd5\u548cUIS\u6d4b\u8bd5\u3002\u5728\u672c\u6b21\u7814\u8ba8\u4f1a\u4e2d\uff0c\u6765\u81ea\u610f\u6cd5\u534a\u5bfc\u4f53\u7684\u7814\u53d1\u4eba\u5458\u5c06\u4e3a\u5927\u5bb6\u4ecb\u7ecd\u5982\u4f55\u4f7f\u7528Silvaco TCAD\u8f6f\u4ef6\u5bf9SiC\u5668\u4ef6\u77ed\u8def\u73b0\u8c61\u8fdb\u884c\u7814\u7a76\u3002<\/div><\/div><\/article>
February 27, 2024<\/div>
Simulation Standard<\/div><\/div>

Advanced TCAD Modeling of HfO2-based ReRAM: Coupling Redox Reactions and Thermal Effects<\/a><\/h3>
This paper presents a TCAD modeling approach for HfO2-based ReRAM (Resistive Random Access Memory). For describing the switching and retention behaviors of\u2026<\/div><\/div><\/article>
February 6, 2024<\/div>
Custom News<\/div><\/div>

Silvaco Expands Sales Channel in Asia – Appoints Vietnam and India Distributors<\/a><\/h3>
Modeling News<\/span>SIPware News<\/span>SPICE News<\/span>TCAD News<\/span>Variation News<\/span><\/div>
February 8, 2024<\/div><\/div><\/article>
January 11, 2024<\/div>
POST<\/div><\/div>

Silvaco TCAD\u89e3\u51b3\u65b9\u6848\u52a9\u529bGaN\u529f\u7387\u5668\u4ef6\u7684\u8bbe\u8ba1\u548c\u5f00\u53d1<\/a><\/h3>
TCAD Webinars<\/span><\/div>
2024\u5e742\u670829\u53f7 \u6211\u4eec\u5c06\u4e3e\u4f8b\u8bf4\u660eSilvaco\u4eff\u771f\u5de5\u5177\u5982\u4f55\u5e2e\u52a9\u7814\u7a76\u4eba\u5458\u8bbe\u8ba1\u3001\u9884\u6d4b\u548c\u5206\u6790\u5782\u76f4\u548c\u6a2a\u5411GaN\u529f\u7387\u5668\u4ef6\u7684\u7535\u7279\u6027\u3002<\/div><\/div><\/article>
January 10, 2024<\/div>
POST<\/div><\/div>

Si\u3001GaN\u548cSiC\u529f\u7387\u5668\u4ef6\u7684SPICE\u5efa\u6a21<\/a><\/h3>
Modeling Webinars<\/span>TCAD Webinars<\/span><\/div>
2024\u5e742\u67088\u53f7 \u6211\u4eec\u5c06\u4e3a\u60a8\u4ecb\u7ecd\u4e0d\u540c\u5236\u9020\u5de5\u827a\u7684\u529f\u7387\u5668\u4ef6\uff0c\u5305\u62ecSi\u3001GaN\u548cSiC\u5668\u4ef6\uff0c\u5206\u6790\u5b83\u4eec\u7684\u7279\u70b9\u548c\u4f18\u52bf\uff0c\u5e76\u5206\u4eab\u5176SPICE\u5efa\u6a21\u7684\u5404\u79cd\u65b9\u6cd5\u548c\u6311\u6218\u3002<\/div><\/div><\/article>
December 20, 2023<\/div>
Custom News<\/div><\/div>

Silvaco Successfully Concludes Its Global Users Event (SURGE) With Over 1000 End-Users and Prospects in Attendance<\/a><\/h3>
Modeling News<\/span>Parasitics+Netlist News<\/span>SIPware News<\/span>SPICE News<\/span>Variation News<\/span><\/div>
December 21, 2023<\/div><\/div><\/article>
September 1, 2023<\/div>
Simulation Standard<\/div><\/div>

Numerical Algorithm to Perform Viscoelastic Analysis<\/a><\/h3>
Numerical Algorithm to Perform Viscoelastic Analysis Viscous materials exhibit both viscous and elastic characteristics when undergoing deformation. The response of such materials\u2026<\/div><\/div><\/article>
August 2, 2023<\/div>
Simulation Standard<\/div><\/div>

2023 TCAD Baseline Release<\/a><\/h3>
New Features in the 2023 Baseline Release: Section 1: Process Simulation \u2013 New Features in 2023 Baseline Release Section 2: Device Simulation\u2026<\/div><\/div><\/article>
July 3, 2023<\/div>
Custom News<\/div><\/div>

SilTerra Leverages Silvaco’s Library Characterization and Optimization Tools to Boost Efficiency in the Development of its Foundry Standard Cell IPs<\/a><\/h3>
Library News<\/span><\/div>
July 6, 2023<\/div><\/div><\/article>
June 6, 2023<\/div>
News<\/div><\/div>

SK Powertech Adopts Silvaco\u2019s Victory TCAD Solution for the Development of Next Generation SiC Power Devices<\/a><\/h3>
June 15, 2023<\/div><\/div><\/article>
May 23, 2023<\/div>
News<\/div><\/div>

Join Us at DAC 2023<\/a><\/h3>
May 24, 2023<\/div><\/div><\/article>
April 24, 2023<\/div>
TCAD Training<\/div><\/div>

Learn How to Use Victory Process TCAD Geometric Etch Models in FinFET and Memory Applications<\/a><\/h3>
TCAD Webinars<\/span><\/div>
May 18, 2023 In this webinar, we present geometric etch models in the context of FinFET and memory applications. We demonstrate techniques\u2026<\/div><\/div><\/article>
April 19, 2023<\/div>
Simulation Standard<\/div><\/div>

Simulation Framework for Device-packaging Co-design for Power Electronics<\/a><\/h3>
The past several years has seen a fast deployment of wide-bandgap power devices in fast chargers, electric vehicles, data centers and renewable\u2026<\/div><\/div><\/article>
March 7, 2023<\/div>
Simulation Standard<\/div><\/div>

Understanding of Geometrical Boundary Conditions in Victory Process<\/a><\/h3>
It is common to run the process simulation for the part of a larger structure just to reduce the computation time. To\u2026<\/div><\/div><\/article>
March 7, 2023<\/div>
POST<\/div><\/div>

Learn About Advanced TFT-Based Flat Panel Design with SmartSpice<\/a><\/h3>
SPICE Webinars<\/span><\/div>
March 23, 2023 In this webinar, we will present the benefits of adopting SmartSpice\u2019s unique 4-terminal TFT compact model, and we describe\u2026<\/div><\/div><\/article>
February 9, 2023<\/div>
Simulation Standard<\/div><\/div>

Automatic Grid Refinement for Thin Material Layer Etching in Process TCAD Simulations<\/a><\/h3>
The utilization of thin material layers is common in modern semiconductor device fabrication. Subsequent etching steps require an accurate modeling of these\u2026<\/div><\/div><\/article>
January 23, 2023<\/div>
POST<\/div><\/div>

Learn How TCAD is a Key Enabler for Photodiode Development<\/a><\/h3>
TCAD Webinars<\/span><\/div>
February 23, 2023 In this webinar, Sungwon Kong will discuss these technologies and how TCAD can be broadly applied to multiple detector\u2026<\/div><\/div><\/article>
January 23, 2023<\/div>
POST<\/div><\/div>

Learn How SilTerra Uses Cello and Viola for Standard Cells and I\/O Library Optimization and Characterization<\/a><\/h3>
SIPware Webinars<\/span><\/div>
February 16, 2023 In this webinar, we will share the challenges of optimizing and validating different libraries, and demonstrate how Cello, Viola,\u2026<\/div><\/div><\/article>
January 13, 2023<\/div>
Simulation Standard<\/div><\/div>

How to Search, View and Use Default Parameters from the Silvaco Material DataBase SMDB with DeckBuild<\/a><\/h3>
Silver, DeckBuild\u2019s material database viewer, can be used to examine the default parameters in the Silvaco Material DataBase (SMDB) and to generate\u2026<\/div><\/div><\/article>
January 10, 2023<\/div>
POST<\/div><\/div>

Learn About the Latest Advances in Device Modeling Using Silvaco Utmost IV<\/a><\/h3>
Modeling Webinars<\/span><\/div>
January 26, 2023 In this webinar, we will introduce the Corner and Retargeting Module, the most recent addition to our modeling software\u2026<\/div><\/div><\/article>
December 13, 2022<\/div>
Simulation Standard<\/div><\/div>

3D TCAD Simulation of Gallium Nitride Tri-gate Junction HEMT<\/a><\/h3>
The GaN high electron mobility transistor (HEMT) has been commercialized as a power device with performance superior to Si devices in the\u2026<\/div><\/div><\/article>
November 1, 2022<\/div>
News<\/div><\/div>

Silvaco Announces Appointment of Five Industry Veterans to Its Board of Directors<\/a><\/h3>
November 8, 2022<\/div><\/div><\/article>
October 27, 2022<\/div>
Simulation Standard<\/div><\/div>

Writing an Impurity Activation Model with the Open Model Library<\/a><\/h3>
Accuracy of Impurity Activation is essential in correctly modeling and simulating Silicon Carbide devices. For high concentrations of dopants, it is well\u2026<\/div><\/div><\/article>
September 16, 2022<\/div>
Simulation Standard<\/div><\/div>

User Probes and Arbitrary Parameter Sweeps in Victory Device<\/a><\/h3>
One of the new features in Victory Device is the ability to add user managed parameters to a log file. This can\u2026<\/div><\/div><\/article>
August 30, 2022<\/div>
POST<\/div><\/div>

Learn About Victory Visual, Silvaco\u2019s New Graphical Visualization Solution for TCAD<\/a><\/h3>
TCAD Webinars<\/span><\/div>
September 22, 2022 In this webinar we will introduce Victory Visual, a new graphical post-processing tool for use with all Silvaco TCAD\u2026<\/div><\/div><\/article>
August 23, 2022<\/div>
Simulation Standard<\/div><\/div>

Quantum Transport Simulation at Atomistic Accuracy of a Nanowire FET<\/a><\/h3>
The FET physical dimensions continue to shrink to five nm node and below, characterized by new types of architectures with nanosheet (NS)\u2026<\/div><\/div><\/article>
August 16, 2022<\/div>
POST<\/div><\/div>

Learn How Victory Atomistic TCAD Solution Can Help You Succeed at Prototyping Atomistic Nanoscale Devices<\/a><\/h3>
TCAD Webinars<\/span><\/div>
September 8, 2022 In this webinar, we present how\u00a0ultra-scaled\u00a0\u00a0Field-Effect Transistor\u00a0(FET) technology requires simulations at the atomic scale for designing the most advanced\u2026<\/div><\/div><\/article>
July 29, 2022<\/div>
Simulation Standard<\/div><\/div>

2022 TCAD Baseline Release<\/a><\/h3>
New Features in the 2022 Baseline Release: Section 1: Process Simulation \u2013 New Features in 2022 Baseline Release Section 2: Device Simulation\u2026<\/div><\/div><\/article>
July 8, 2022<\/div>
POST<\/div><\/div>

Learn How to Efficiently Achieve Accurate Experimental Etch Profiles in FinFET and Memory Applications with Victory TCAD Solution<\/a><\/h3>
TCAD Webinars<\/span><\/div>
August 11, 2022 In this webinar, we present these geometric etch models in the context of FinFET and memory applications. We demonstrate\u2026<\/div><\/div><\/article>
June 17, 2022<\/div>
\u672a\u5206\u7c7b<\/div><\/div>

Join Us at DAC 2022<\/a><\/h3>
Join Us at DAC 2022 Join us at 2022 Design Automation Conference where we will highlight the company\u2019s wide range of semiconductor\u2026<\/div><\/div><\/article>
June 14, 2022<\/div>
Simulation Standard<\/div><\/div>

Simulation of the High Temperature Performance of InGaN \u2018Topping\u2019 Cells<\/a><\/h3>
This work reports on the design of a high efficiency InGaN-based two junction (2J) tandem solar cell via numerical simulation, operating at\u2026<\/div><\/div><\/article>
June 13, 2022<\/div>
POST<\/div><\/div>

Learn How Silvaco Flow Helps Designing and Simulating Pixel Arrays in Flat Panel Displays and Detectors<\/a><\/h3>
SPICE Webinars<\/span>TCAD Webinars<\/span><\/div>
June 30, 2022 In this webinar, we highlight how leading display and detector companies exploit the capabilities of Silvaco tools for schematic\u2026<\/div><\/div><\/article>
May 19, 2022<\/div>
Custom Webinars<\/div><\/div>

How to Eliminate Image Retention Issues with SmartSpice Flex Modeling<\/a><\/h3>
SPICE Webinars<\/span><\/div>
June 9, 2022 In this webinar, we will introduce a solution to the long-standing issue in the display community of Image Retention\u2026<\/div><\/div><\/article>
May 3, 2022<\/div>
Simulation Standard<\/div><\/div>

Investigation of Self-Heating Effects in SOI MOSFETs with Silvaco Numerical Simulation<\/a><\/h3>
Self-heating effect may cause over-heated damage and degradation for silicon-on-insulator (SOI) devices, so numerical counting heat generated, and distribution can optimize the\u2026<\/div><\/div><\/article>
April 26, 2022<\/div>
POST<\/div><\/div>

Learn About Silvaco\u2019s AMBA AHB Subsystems and How to Customize, Secure, and Verify<\/a><\/h3>
SIPware Webinars<\/span><\/div>
May 12, 2022 In this webinar, we will provide an overview of the AMBA AHB subsystems and products offered by Silvaco. Some\u2026<\/div><\/div><\/article>
April 11, 2022<\/div>
Custom Webinars<\/div><\/div>

Learn How to Improve TFT-Based Flat Panel Designs with the Unique SmartSpice 4-Terminal TFT Model<\/a><\/h3>
SPICE Webinars<\/span><\/div>
April, 28, 2022 (PDT) In this webinar, we\u00a0will describe SmartSpice\u2019s 4-terminal TFT compact model. Unique in the market, we present some of\u2026<\/div><\/div><\/article>
April 1, 2022<\/div>
Simulation Standard<\/div><\/div>

How Can I Remesh a Structure Using a Custom Volume Mesh in Victory Mesh?<\/a><\/h3>
Victory Mesh support for line statements lets the user customize the volume mesh used by conformal remesh schemes. The volume mesh data\u2026<\/div><\/div><\/article>
March 9, 2022<\/div>
POST<\/div><\/div>

Learn How mqSemi AG Developed 3D Power Devices Proof of Concept with Silvaco TCAD Simulations<\/a><\/h3>
TCAD Webinars<\/span><\/div>
March 24, 2022 | 10:00 am \u2013 10:30 am (PDT) In this Webinar, we will introduce mqSemi and the 3D TCAD models\u2026<\/div><\/div><\/article>
March 3, 2022<\/div>
Simulation Standard<\/div><\/div>

Simulation of AlGaInP Multiple Quantum Well LED for Micro Display<\/a><\/h3>
The flat panel display industry has been growing rapidly for recent years in mobile display, car display, AR\/VR applications, and large-scale TVs\u2026<\/div><\/div><\/article>
March 1, 2022<\/div>
POST<\/div><\/div>

How Silvaco TCAD is at the Heart of Innovation in RF Devices<\/a><\/h3>
TCAD Webinars<\/span><\/div>
March 17, 2022 | 10:00 am \u2013 10:30 am (PDT) In this Webinar, Silvaco\u2019s TCAD Victory Device simulation tool is used to\u2026<\/div><\/div><\/article>
February 28, 2022<\/div>
News<\/div><\/div>

Silvaco Announces that Teledyne e2v Expands Adoption of its Victory TCAD Solution to Further Accelerate Development of CMOS Image Sensors<\/a><\/h3>
TCAD News<\/span><\/div>
March 2, 2022<\/div><\/div><\/article>
February 22, 2022<\/div>
POST<\/div><\/div>

How to Optimize and Boost Your Device Modeling and Characterization with Utmost IV<\/a><\/h3>
Modeling Webinars<\/span><\/div>
March 10, 2022 | 10:00 am \u2013 10:30 am (PST) In this webinar we will examine some of the key features and\u2026<\/div><\/div><\/article>
February 1, 2022<\/div>
Simulation Standard<\/div><\/div>

Relating Platinum Diffusion to Minority Carrier Lifetime Control in PiN Diode: Coupled TCAD Process and Device Simulation<\/a><\/h3>
Platinum and gold are widely used as an effective method to control lifetime in silicon-based devices [1, 2, 3]. Platinum and gold\u2026<\/div><\/div><\/article>
January 21, 2022<\/div>
TCAD Training<\/div><\/div>

How to Use Device Simulation as a Tool for Understanding GaN HEMTs<\/a><\/h3>
TCAD Webinars<\/span><\/div>
February 24, 2022 | 10:00 am \u2013 10:30 am (PST) This webinar will illustrate through specific published examples of how TCAD device\u2026<\/div><\/div><\/article>
January 21, 2022<\/div>
Custom Webinars<\/div><\/div>

How to Improve Physical Verification Productivity with SmartDRC\/LVS<\/a><\/h3>
February 17, 2022 | 10:00 am \u2013 10:30 am (PST) Physical Verification is the most critical stage of microchip design. This webinar\u2026<\/div><\/div><\/article>
January 6, 2022<\/div>
Simulation Standard<\/div><\/div>

Enabling the Rapid Development of SiC Superjunction-MOSFETs in Collaboration with mi2-factory<\/a><\/h3>
Introduction Super-junction based devices are a key enabling technology for power devices. Adjacent columns of p and n-type doped material with optimized\u2026<\/div><\/div><\/article>
December 13, 2021<\/div>
Custom News<\/div><\/div>

Colin Shaw of Silvaco Named Si2 Pinnacle Award Winner<\/a><\/h3>
Foundation IP News<\/span>Library News<\/span>Modeling News<\/span>Parasitics+Netlist News<\/span>SIPware News<\/span>SPICE News<\/span>TCAD News<\/span>Variation News<\/span><\/div>
December 12, 2021<\/div><\/div><\/article>
November 1, 2021<\/div>
Simulation Standard<\/div><\/div>

TCAD Modeling of Amorphous Selenium-based Avalanche Photon Detectors<\/a><\/h3>
Abstract\u2014 Silvaco TCAD simulations are employed to identify relevant current carrying mechanisms in amorphous selenium (a-Se) based detectors, using parameters obtained from\u2026<\/div><\/div><\/article>
October 20, 2021<\/div>
Silvaco<\/div><\/div>

Strategic Account Manager<\/a><\/h3>
Location: Seattle\/Bellevue, WA - Boston, MA - Phoenix\/San Diego, CA As a Strategic Account Manager at Silvaco, you will be responsible for\u2026<\/div><\/div><\/article>
October 1, 2021<\/div>
Simulation Standard<\/div><\/div>

Singular Point Source MOS Cell Concept (S-MOS) Implemented on a Narrow Mesa Trench IGBT<\/a><\/h3>
Abstract\u2014 A Singular Point Source MOS (S-MOS) cell concept suitable for power MOS based devices is presented. The S-MOS differs from a\u2026<\/div><\/div><\/article>
September 16, 2021<\/div>
Simulation Standard<\/div><\/div>

Singular Point Source MOS Cell Concept (S-MOS) Implemented on a Narrow Mesa Trench IGBT<\/a><\/h3>
Abstract\u2014 A Singular Point Source MOS (S-MOS) cell concept suitable for power MOS based devices is presented. The S-MOS differs from a\u2026<\/div><\/div><\/article>
September 16, 2021<\/div>
Simulation Standard<\/div><\/div>

A Comprehensive Oxide-Based ReRAM TCAD Model with Experimental Verification<\/a><\/h3>
Abstract\u2014During the last few years, oxide-based ReRAM technology has attracted intense industrial and scientific research interest. Therefore, we have performed an in-depth\u2026<\/div><\/div><\/article>
September 2, 2021<\/div>
News<\/div><\/div>

iDEAL Semiconductor Adopts Silvaco Victory TCAD\u00a0Solution\u00a0for the Development of Next-Gen High Efficiency Power Devices\u00a0<\/a><\/h3>
TCAD News<\/span><\/div>
Sept 2, 2021<\/div><\/div><\/article>
August 17, 2021<\/div>
POST<\/div><\/div>

Designing with Silvaco’s Octal SPI Memory Controller with Advanced Memory Support for IoT Systems<\/a><\/h3>
SIPware Webinars<\/span><\/div>
September 9, 2021 | 10:00 am \u2013 10:30 am (PDT) This webinar will focus on a specific class of memory devices \u2013\u2026<\/div><\/div><\/article>
July 27, 2021<\/div>
POST<\/div><\/div>

Silvaco SmartSpice 2021 – Top 10 New Features in the Baseline Release<\/a><\/h3>
SPICE Webinars<\/span><\/div>
August 19, 2021 | 10:00 am \u2013 10:30 am (PDT) In this webinar, we present the top 10 new features and improvements\u2026<\/div><\/div><\/article>
July 22, 2021<\/div>
Simulation Standard<\/div><\/div>

2021 TCAD Baseline Release<\/a><\/h3>
New Features in 2021 Baseline Release: Section 1: Process Simulation Section 2: Device Simulation Section 3: Victory Mesh Section 4: Parasitic Extraction<\/div><\/div><\/article>
July 12, 2021<\/div>
POST<\/div><\/div>

100X Faster Nano Device Atomistic TCAD Simulation with Victory Atomistic<\/a><\/h3>
TCAD Webinars<\/span><\/div>
August 5, 2021 | 10:00 am \u2013 10:30 am (PDT) In this webinar you will learn about 100X Faster Nano Device Atomistic\u2026<\/div><\/div><\/article>
June 23, 2021<\/div>
POST<\/div><\/div>

Simulation of Silicon and Perovskite Based Tandem Solar Cells Using TCAD<\/a><\/h3>
TCAD Webinars<\/span><\/div>
July 15, 2021 | 10:00 am \u2013 10:35 am (PDT)\u2028 In this webinar you will learn Simulation of Silicon and Perovskite Based\u2026<\/div><\/div><\/article>
June 15, 2021<\/div>
Simulation Standard<\/div><\/div>

An Introduction to Meshing in Victory Process<\/a><\/h3>
Victory Process (VP) uses two types of mesh to represent the structure: \u2022 The geometry mesh, which is used to represent the\u2026<\/div><\/div><\/article>
June 10, 2021<\/div>
Custom Webinars<\/div><\/div>

Achieve Your Display Design Performance Edge Through Precision Parasitic Extraction<\/a><\/h3>
TCAD Webinars<\/span><\/div>
June 29, 2021 | 10:00 am \u2013 10:30 am (PDT) In this webinar you will learn how Silvaco Hipex-FS can help designers\u2026<\/div><\/div><\/article>
June 3, 2021<\/div>
POST<\/div><\/div>

Achieving Extreme Low Power IoT Designs with Silvaco\u2019s 55LPx Foundation IP Solution<\/a><\/h3>
SIPware Webinars<\/span><\/div>
June 24, 2021 | 10:00 am \u2013 10:30 am (PDT) \u2028In this webinar you will learn how Silvaco Foundation IP helps you\u2026<\/div><\/div><\/article>
May 28, 2021<\/div>
POST<\/div><\/div>

Oxide Semiconductor LSI Technology and SPICE Model for Ultra Low Power LSI<\/a><\/h3>
Modeling Webinars<\/span><\/div>
May 12, 2021 | 13:00-13:40 (JST) In this webinar, we will introduce CAAC-IGZO\u24c7 FET (c-axis aligned crystalline indium-gallium-zinc oxide FET) developed by\u2026<\/div><\/div><\/article>
May 21, 2021<\/div>
Simulation Standard<\/div><\/div>

Compact Multi-Level Digital-to-Analog Conversion Using Thin-Film Multimodal Transistors<\/a><\/h3>
Unlike conventional ohmic contact thin-film transistors (TFTs), contact-controlled TFTs [1], [2] rely on source energy barriers to produce a range of benefits\u2026<\/div><\/div><\/article>
May 12, 2021<\/div>
\u672a\u5206\u7c7b<\/div><\/div>

2021 TSMC Worldwide Technology Symposium<\/a><\/h3>
Welcome! Thank You for visiting our virtual booth at the 2021 TSMC Worldwide Technology Symposium. We hope you found the information useful\u2026<\/div><\/div><\/article>
May 12, 2021<\/div>
POST<\/div><\/div>

Development & Delivery of Complete IO & ESD Library in 5 Weeks<\/a><\/h3>
SIPware Webinars<\/span><\/div>
June 3, 2021 | 10:00 am \u2013 10:30 am (PDT) \u2028In this webinar, you will learn development & delivery of complete IO\u2026<\/div><\/div><\/article>
May 11, 2021<\/div>
News<\/div><\/div>

Media Alert: Weebit Nano and Silvaco to Present Latest ReRAM Modeling Developments at IMW 2021<\/a><\/h3>
TCAD News<\/span><\/div>
May 11, 2021<\/div><\/div><\/article>
May 7, 2021<\/div>
POST<\/div><\/div>

GaN-Based LEDs – Combining Process and Device TCAD to Optimize Substrate Patterning and Maximize Light Extraction Efficiency<\/a><\/h3>
TCAD Webinars<\/span><\/div>
May 20, 2021 | 10:00 am \u2013 10:30 am (PDT) \u2028In this webinar, a workflow that combines process and device TCAD to\u2026<\/div><\/div><\/article>
April 29, 2021<\/div>
Custom Webinars<\/div><\/div>

How to Model and Simulate Flat Panel Pixel Arrays<\/a><\/h3>
Modeling Webinars<\/span>SPICE Webinars<\/span><\/div>
\u00a0May 13, 2021 | 10:00 am \u2013 10:35 am (PDT) In this webinar we will look at some of the effects to\u2026<\/div><\/div><\/article>
April 19, 2021<\/div>
Simulation Standard<\/div><\/div>

Investigation and Explanation of PiPiN Avalanche Photo-Diode Characteristics<\/a><\/h3>
In this article, the operation of avalanche photo-diodes in the medium gain, continuous operation mode is investigated. In other words, we are\u2026<\/div><\/div><\/article>
April 19, 2021<\/div>
POST<\/div><\/div>

How to Modify Material and Modeling Properties with Silvaco Victory TCAD Solution<\/a><\/h3>
TCAD Webinars<\/span><\/div>
\u00a0May 6, 2021 | 10:00 am \u2013 10:35 am (PDT) In this webinar we will demonstrate how to set models for simulations,\u2026<\/div><\/div><\/article>
April 14, 2021<\/div>
Custom News<\/div><\/div>

Semiconductor Energy Laboratory and Silvaco Jointly Develop SPICE Model of Oxide Semiconductor FETs<\/a><\/h3>
April 14, 2021<\/div><\/div><\/article>
April 5, 2021<\/div>
Custom Webinars<\/div><\/div>

How to Accelerate Post-layout Parasitics Analysis and Avoid Wasted Simulation Cycles<\/a><\/h3>
SPICE Webinars<\/span><\/div>
April 20, 2021 | 10:00 am \u2013 10:30 am (PDT) In this webinar we will show how to accelerate post-layout parasitics analysis\u2026<\/div><\/div><\/article>
March 25, 2021<\/div>
POST<\/div><\/div>

How to Build a New Diffusion Model with Silvaco Victory TCAD Solution<\/a><\/h3>
TCAD Webinars<\/span><\/div>
April 8, 2021 | 10:00 am \u2013 10:30 am (PDT) In this webinar we will demonstrate how to create a custom diffusion\u2026<\/div><\/div><\/article>
March 4, 2021<\/div>
Simulation Standard<\/div><\/div>

How do I create complex shapes with fixed cross sections in Victory Mesh?<\/a><\/h3>
Victory Mesh versions 1.7.2.C and later include two new commands that can be used for complex shape genera-tion. The path and follow\u2026<\/div><\/div><\/article>
March 4, 2021<\/div>
\u672a\u5206\u7c7b<\/div><\/div>

GOMAC 2021<\/a><\/h3>
Welcome! Thank You for visiting our booth at GOMAC 2021. We hope you found the information useful and informative. Enter drawing to\u2026<\/div><\/div><\/article>
February 24, 2021<\/div>
\u672a\u5206\u7c7b<\/div><\/div>

RF Algorithm Engineer<\/a><\/h3>
Location: Moscow, Kiev Ukraine, UK, Grenoble Silvaco is one of a few providers of highly sophisticated software for electronic circuit simulation. With\u2026<\/div><\/div><\/article>
February 16, 2021<\/div>
\u672a\u5206\u7c7b<\/div><\/div>

Learn How Silvaco\u2019s SmartSpice is Getting Faster<\/a><\/h3>
When: March 4, 2021 Where: Online Time: 10:00am-10:20am-(PST) Language: English Register to Win!! Enter drawing to win an Amazon gift card Learn\u2026<\/div><\/div><\/article>
February 3, 2021<\/div>
Simulation Standard<\/div><\/div>

Parabolic Grading of a PHEMT Channel Composition for Ultra-High and Broad OIP3 Peak<\/a><\/h3>
We detect a local maximum in the design space of a pseudomorphic-channel high electron mobility transistor (PHEMT). The design has an OIP3\u00a0\u2026<\/div><\/div><\/article>
January 20, 2021<\/div>
News<\/div><\/div>

Silvaco Acquires Physical Verification Solution Provider POLYTEDA CLOUD LLC<\/a><\/h3>
Modeling News<\/span>Modeling Press<\/span>SPICE News<\/span><\/div>
January 21, 2021<\/div><\/div><\/article>
January 18, 2021<\/div>
POST<\/div><\/div>

Accelerating Wireless IOT SoC Implementation with Silvaco AMBA\u00ae Subsystem IP<\/a><\/h3>
SIPware Webinars<\/span><\/div>
January 28, 2021 | 10:00 am \u2013 10:30 am (PST) In this webinar you will learn how Rafael Microelectronics has deployed Silvaco\u2019s\u2026<\/div><\/div><\/article>
January 17, 2021<\/div>
POST<\/div><\/div>

How to Design Wide Band-Gap Power Devices using Silvaco TCAD Solution<\/a><\/h3>
TCAD Webinars<\/span><\/div>
February 11, 2021 | 10:00 am \u2013 10:20 am (PST) This webinar will provide an overview of the design of wide bandgap\u2026<\/div><\/div><\/article>
January 17, 2021<\/div>
POST<\/div><\/div>

How To Remesh with Victory Mesh for an Optimized TCAD Device Simulation<\/a><\/h3>
TCAD Webinars<\/span><\/div>
February 18, 2021 | 10:00 am \u2013 11:00 am (PST) In this webinar, the attendees will learn the basics of Victory Mesh,\u2026<\/div><\/div><\/article>
January 17, 2021<\/div>
POST<\/div><\/div>

How to Design Ultra-low Power Embedded Memories with Silvaco Memory Compilers<\/a><\/h3>
SIPware Webinars<\/span><\/div>
February 23, 2021 | 10:00 am \u2013 10:30 am (PST) This webinar presents Silvaco\u2019s Embedded Memory offerings as part of a complete\u2026<\/div><\/div><\/article>
January 15, 2021<\/div>
Custom Webinars<\/div><\/div>

Learn How Silvaco\u2019s SmartSpice is Getting Faster<\/a><\/h3>
SPICE Webinars<\/span><\/div>
March 4, 2021 | 10:00 am \u2013 10:20 am (PST) In this Webinar, we present (1) a general overview of SmartSpice, our\u2026<\/div><\/div><\/article>
January 14, 2021<\/div>
POST<\/div><\/div>

How to Quickly Achieve Accurate SPICE Models with Utmost IV<\/a><\/h3>
Modeling Webinars<\/span>SPICE Webinars<\/span><\/div>
March 16, 2021 | 10:00 am \u2013 10:20 am (PST) This webinar will review the various Silvaco SPICE modeling solutions. This includes\u2026<\/div><\/div><\/article>
January 13, 2021<\/div>
POST<\/div><\/div>

How to Simulate Semiconductor Materials Stress and Deformation with Silvaco Victory TCAD Solution<\/a><\/h3>
TCAD Webinars<\/span><\/div>
March 18, 2021 | 10:00 am \u2013 10:30 am (PST) In this webinar we will cover the capabilities and usage of Victory\u2026<\/div><\/div><\/article>
January 12, 2021<\/div>
\u672a\u5206\u7c7b<\/div><\/div>

Etching & Deposition Software Engineer<\/a><\/h3>
Location: United Kingdom, Grenoble France, Vienna Austria, Germany, Boston, MA, Duluth, GA, and Santa Clara, CA. As a member of the TCAD\u2026<\/div><\/div><\/article>
January 4, 2021<\/div>
Simulation Standard<\/div><\/div>

TCAD Investigation of Total Ionizing Dose (TID) Effects on Gallium Nitride HEMTs<\/a><\/h3>
Gallium Nitride (GaN) based devices such as the High Electron Mobility Transistors (HEMTs) find wide applications in RF and Power domain due\u2026<\/div><\/div><\/article>
December 14, 2020<\/div>
POST<\/div><\/div>

Reducing the Layout Development Cycle Time for Standard Cells<\/a><\/h3>
SIPware Webinars<\/span><\/div>
January 14, 2021 | 10:00 am \u2013 10:20 am (PST) In this webinar, Sharmistha Sinha and Anand Mishra share their analysis and\u2026<\/div><\/div><\/article>
December 8, 2020<\/div>
Custom Webinars<\/div><\/div>

Good News \u2013 The Silvaco Analog Custom Design Flow<\/a><\/h3>
SPICE Webinars<\/span><\/div>
December 17, 2020 | 10:00 am \u2013 10:15 am (PST) In this webinar, we describe Silvaco\u2019s Analog Custom Design solution and how\u2026<\/div><\/div><\/article>
December 2, 2020<\/div>
Simulation Standard<\/div><\/div>

Obtaining Spectral Sweeps from 3D Plasmonic Structures<\/a><\/h3>
In the simulation standard article, \u201cPlasmonic Light Trapping Transforming Thin-Film Photovoltaics\u201d from 2015, the finite difference time domain (FDTD) algorithm was used\u2026<\/div><\/div><\/article>
November 24, 2020<\/div>
Corporate Blog<\/div><\/div>

Worldwide Success for Virtual Silvaco UseRs Global Events (SURGE)<\/a><\/h3>
In late October and early November 2020, Silvaco held its fourth annual series of UseRs Global Events (SURGE). Because of the current\u2026<\/div><\/div><\/article>
November 24, 2020<\/div>
News<\/div><\/div>

IRIS Switzerland Adopts Silvaco TCAD Software for the Development of Photodiodes for Autonomous Driving Applications<\/a><\/h3>
TCAD News<\/span><\/div>
November 24, 2020<\/div><\/div><\/article>
November 18, 2020<\/div>
Corporate Blog<\/div><\/div>

Silvaco Presents at 13th International MOS-AK Virtual Workshop, Dec. 10 – 11<\/a><\/h3>
The\u00a013th International MOS-AK Workshop will be hosted virtually on December 10 and 11, 2020, and Silvaco R&D will be presenting. The\u00a0MOS-AK Workshop\u00a0aims\u2026<\/div><\/div><\/article>
November 12, 2020<\/div>
News<\/div><\/div>

Silvaco Acquires Memory Compiler Technology of Dolphin Design SAS<\/a><\/h3>
SIPware News<\/span><\/div>
November 12, 2020 Silvaco Inc., a leading supplier of EDA software and design IP, today announced that it has completed the acquisition\u2026<\/div><\/div><\/article>
October 28, 2020<\/div>
Custom Blogs<\/div><\/div>

Customer Interview: Why I Rely on SmartSpice<\/a><\/h3>
SPICE Blogs<\/span><\/div>
Martin Mallinson is an experienced analog circuit designer with multiple patents. Over his 40-year career, his audio designs have been used in\u2026<\/div><\/div><\/article>
October 28, 2020<\/div>
Corporate Blog<\/div><\/div>

Silvaco’s Babak Taheri Speaking @ MEMS World Summit Shanghai, Nov. 17<\/a><\/h3>
MEMS World Summit is the world\u2019s foremost annual meeting and business platform for engaging with political, business, financial, research and industry leaders\u2026<\/div><\/div><\/article>
October 26, 2020<\/div>
POST<\/div><\/div>

Application Engineer, SPICE Modeling<\/a><\/h3>
Location Atlanta, GA Silvaco seeks an experienced Application Engineer with a strong background in electrical device measurement and characterization, and in SPICE\u2026<\/div><\/div><\/article>
October 26, 2020<\/div>
POST<\/div><\/div>

Simulate 40X Faster with SmartSpice HPP<\/a><\/h3>
SPICE Webinars<\/span><\/div>
In this webinar, we describe how\u00a0SmartSpice\u00a0HPP takes advantage of the modern multicore hardware platforms to speed up all internal aspects of transient\u2026<\/div><\/div><\/article>
October 1, 2020<\/div>
Simulation Standard<\/div><\/div>

Optimizing a 2um, 1,500 Volt SiC Superjunction Trench-MOS Device Using TCAD<\/a><\/h3>
In this paper the critical design features of a SiC superjunction trench MOS device were optimized using CAD to obtain a high\u2026<\/div><\/div><\/article>
October 1, 2020<\/div>
Simulation Standard<\/div><\/div>

TCAD Simulation of CBRAM Devices<\/a><\/h3>
Conductive Bridge Random Access Memory (CBRAM) is a non-volatile memory device technology that can operate by consuming very low power. Another advantage\u2026<\/div><\/div><\/article>
October 1, 2020<\/div>
Simulation Standard<\/div><\/div>

TCAD Mixed-Mode Simulation for GaN Power HEMTs in Unclamped Inductive Switching<\/a><\/h3>
The qualification of GaN power high-electron-mobilitytransistors (HEMTs) must consider the device ruggedness against out-of-SOA (safe operating area) events [1- 3].<\/div><\/div><\/article>
October 1, 2020<\/div>
Simulation Standard<\/div><\/div>

Using Victory Process Open Model Interface to Customize Etch Emulation Model \u2013 Example<\/a><\/h3>
Dry etching is commonly used in semiconductor processing to generate deep trenches with good anisotropy. Dry etching is applied to many semiconductor\u2026<\/div><\/div><\/article>
September 9, 2020<\/div>
News<\/div><\/div>

Silvaco Acquires the Assets of Coupling Wave Solutions S.A.<\/a><\/h3>
SIPware News<\/span><\/div>
September 9, 2020<\/div><\/div><\/article>
September 3, 2020<\/div>
POST<\/div><\/div>

Improvement of Parasitic Capacitance Extraction Rules for Large-Scale Layout and Its Accuracy Verification Method<\/a><\/h3>
Parasitics+Netlist Webinars<\/span><\/div>
September 17, 2020 | 13:00 \u2013 13:30 (JST) The accuracy of rule-based full-chip parasitic capacitance extraction tools including Silvaco's Hipex is highly\u2026<\/div><\/div><\/article>
September 3, 2020<\/div>
POST<\/div><\/div>

Choosing the Right DDR Memory Subsystem for Your Next SOC!<\/a><\/h3>
SIPware Webinars<\/span><\/div>
October 13, 2020 | 10:00 am \u2013 10:30 am (PST) As computation requirements continue to build and memory systems are operating at\u2026<\/div><\/div><\/article>
September 2, 2020<\/div>
TCAD<\/div><\/div>

Silvaco at Upcoming Solid-State Conferences – ESSDERC 2020 and SISPAD 2020<\/a><\/h3>
TCAD Blogs<\/span><\/div>
Silvaco technologists and research partners will be participating in the ESSDERC\/ESSCIRC 2020 joint conference for solid-state devices and circuits.\u00a0 Tutorial #8, Ab-initio\u2026<\/div><\/div><\/article>
August 25, 2020<\/div>
News<\/div><\/div>

SemiQ Switches to Silvaco TCAD for Design of Power Devices<\/a><\/h3>
TCAD News<\/span><\/div>
August 26, 2020<\/div><\/div><\/article>
July 31, 2020<\/div>
Simulation Standard<\/div><\/div>

2020 TCAD Baseline Release Section 1: Process Simulation \u2013 New Features in 2020 Baseline Release<\/a><\/h3>
2020 TCAD Baseline Release Section 1: Process Simulation \u2013 New Features in 2020 Baseline Release<\/div><\/div><\/article>
July 31, 2020<\/div>
Simulation Standard<\/div><\/div>

2020 TCAD Baseline Release Section 2: Meshing \u2013 New Features in 2020 Baseline Release<\/a><\/h3>
2020 TCAD Baseline Release Section 2: Meshing \u2013 New Features in 2020 Baseline Release<\/div><\/div><\/article>
July 31, 2020<\/div>
Simulation Standard<\/div><\/div>

2020 TCAD Baseline Release – Device Simulation \u2013 New Features in 2020 Baseline Release<\/a><\/h3>
2020 TCAD Baseline Release Section 3: Device Simulation \u2013 New Features in 2020 Baseline Release<\/div><\/div><\/article>
July 25, 2020<\/div>
POST<\/div><\/div>

High speed Interface Design: Best Practices<\/a><\/h3>
SIPware Webinars<\/span><\/div>
August 27, 2020 | 10:00 am \u2013 10:30 am (PDT) This webinar will provide a presentation on challenges and solutions associated with\u2026<\/div><\/div><\/article>
July 20, 2020<\/div>
Corporate Blog<\/div><\/div>

CEO Perspective \u2013 Challenges and Opportunities for Global Semiconductor Businesses<\/a><\/h3>
by Babak Taheri, Silvaco CEO In 1966 Robert F. Kennedy delivered a speech that mentioned a curse, \u201cMay you live in interesting\u2026<\/div><\/div><\/article>
July 9, 2020<\/div>
POST<\/div><\/div>

How to Secure an AMBA AHB Subsystem for the ARM Cortex M3 Processor<\/a><\/h3>
SIPware Webinars<\/span><\/div>
July 28, 2020 | 10:00 am \u2013 10:30 am (PDT) This webinar will provide a discussion of common methods used to secure\u2026<\/div><\/div><\/article>
July 7, 2020<\/div>
POST<\/div><\/div>

Model Extraction Flow with Utmost IV for Vertically Stacked Nanosheets Using the Leti-NSP Model<\/a><\/h3>
Modeling Webinars<\/span><\/div>
July 30, 2020 | 10:00 am \u2013 10:30 am (PDT) This webinar will provide a discussion of common methods used to secure\u2026<\/div><\/div><\/article>
July 6, 2020<\/div>
Corporate Blog<\/div><\/div>

Replay of 2020 ESD Alliance CEO Outlook Panel<\/a><\/h3>
The ESD Alliance CEO Outlook was held on June 17, 2020. This year\u2019s informative event, featuring six prominent industry CEOs, was conducted\u2026<\/div><\/div><\/article>
May 28, 2020<\/div>
POST<\/div><\/div>

Samsung Foundry and Silvaco Design IP: The Right Solution for Your Next SoC!<\/a><\/h3>
SIPware Webinars<\/span><\/div>
May 28, 2020 | 10:00 am \u2013 10:30 am (PDT) In this webinar, we will provide a thorough introduction to Samsung Foundry\u2026<\/div><\/div><\/article>
May 21, 2020<\/div>
POST<\/div><\/div>

Using SmartSpice Compact Models<\/a><\/h3>
Modeling Webinars<\/span>SPICE Webinars<\/span><\/div>
June 11, 2020 | 10:00 am \u2013 10:30 am (PDT) This webinar will provide a guide to developing Compact Models in SmartSpice\u2026<\/div><\/div><\/article>
May 21, 2020<\/div>
POST<\/div><\/div>

Resistive RAM Switching Analysis with Victory TCAD Solution<\/a><\/h3>
TCAD Webinars<\/span><\/div>
June 4, 2020 | 10:00 am \u2013 10:30 am (PDT) Conventional non-volatile memory technologies, such as Flash, are near their physical limits\u2026<\/div><\/div><\/article>
May 20, 2020<\/div>
POST<\/div><\/div>

Machine Learning in the EDA-Specific Domain – 20 Years in the Making<\/a><\/h3>
Modeling Webinars<\/span>Variation Webinars<\/span><\/div>
June 25, 2020 | 10:00 am \u2013 10:30 am (PDT) This webinar will review these new approaches and how they are applied\u2026<\/div><\/div><\/article>
April 20, 2020<\/div>
POST<\/div><\/div>

TFT and OLED SPICE Modeling Using Utmost IV<\/a><\/h3>
Modeling Webinars<\/span><\/div>
May 14th 2020 | 10:00 am \u2013 10:30 am (PDT) In this webinar you will learn about SPICE modeling approaches and methods\u2026<\/div><\/div><\/article>
April 20, 2020<\/div>
Webinars for Display Week<\/div><\/div>

Optoelectronic Simulation of Solar Cells, Waveguides, and LEDs<\/a><\/h3>
TCAD Webinars<\/span><\/div>
April 23nd 2020 | 10:00 am \u2013 11:00 am (PDT) In this webinar, we will give an overview of Silvaco\u2019s optical simulation\u2026<\/div><\/div><\/article>
April 7, 2020<\/div>
Analog Custom Design<\/div><\/div>

Silvaco Licenses HiSIM_IGBT Power Device Model Developed by HiSIM Consortium and Provides Support in SmartSpice Circuit Simulator<\/a><\/h3>
Modeling News<\/span>Modeling Press<\/span>SPICE News<\/span>SPICE Press<\/span><\/div>
April 7, 2020<\/div><\/div><\/article>
April 2, 2020<\/div>
News<\/div><\/div>

Trixell Adopts Silvaco TCAD-based Parasitic Extraction Solution for Development of New Display Technology<\/a><\/h3>
TCAD News<\/span><\/div>
April 2, 2020<\/div><\/div><\/article>
March 30, 2020<\/div>
POST<\/div><\/div>

Accelerating Design with the Victory TCAD Suite<\/a><\/h3>
TCAD Blogs<\/span><\/div>
The Simulation Standard, Silvaco\u2019s technical journal for semiconductor process and device engineers is beginning its 30th year of publication. The latest issue\u2026<\/div><\/div><\/article>
March 30, 2020<\/div>
News<\/div><\/div>

Silvaco Delivers New Generation of MIPI I3C\u00ae Sensor Connectivity IP<\/a><\/h3>
SIPware News<\/span><\/div>
March 30, 2020<\/div><\/div><\/article>
March 9, 2020<\/div>
Webinars for Display Week<\/div><\/div>

Reducing Organic LED Fabrication Time and Cost via Multi-Scale Flow Simulation<\/a><\/h3>
TCAD Webinars<\/span><\/div>
April 2nd 2020 | 10:00 am \u2013 11:00 am (PDT) Drift diffusion simulations are widely applied to study multilayer organic LED devices,\u2026<\/div><\/div><\/article>
March 3, 2020<\/div>
Simulation Standard<\/div><\/div>

Victory TCAD Suite: How to use it for fast, efficient, and accurate simulation of power semiconductor devices<\/a><\/h3>
Silvaco TCAD has been used by Tier 1 power device manufactures and designers for decades. The introduction of Victory Process, Victory Mesh,\u2026<\/div><\/div><\/article>
March 2, 2020<\/div>
POST<\/div><\/div>

TCAD Simulations of RF-SOI Switches with Trap-Rich Substrate<\/a><\/h3>
TCAD Blogs<\/span><\/div>
The market for cellular components has been shifting rapidly from GaAs pHEMT or silicon-on-sapphire (SOS) to silicon-based technology. CMOS (silicon-on-insulator) SOI antenna\u2026<\/div><\/div><\/article>
March 2, 2020<\/div>
Simulation Standard<\/div><\/div>

Hints and Tips: Specify Units in the Victory Process Material Statement<\/a><\/h3>
It is crucial for any kind of calculations that units are consistent between equations and modeling modules. Often different units are used\u2026<\/div><\/div><\/article>
March 1, 2020<\/div>
POST<\/div><\/div>

Utmost IV Quick-Start Model Optimization Templates<\/a><\/h3>
Modeling Webinars<\/span><\/div>
March 12th 2020 | 10:00 am - 11:00 am (PDT) This webinar will present a new capability available in UTMOST IV: the\u2026<\/div><\/div><\/article>
March 1, 2020<\/div>
Simulation Standard<\/div><\/div>

Hints and Tips: How do I Load, Remesh, and Refine an Existing Device Structure in Victory Mesh?<\/a><\/h3>
Victory Mesh initially supported loading and remeshing of the saved status from Victory Process. Victory Mesh 1.5.0 onwards is now able to\u2026<\/div><\/div><\/article>
February 26, 2020<\/div>
Technical Libraries<\/div><\/div>

Nanoscale Devices<\/a><\/h3>
Nanoscale Devices<\/span>TCAD Published Papers<\/span><\/div>
Nanoscale Devices The full text for most of these papers may be found at the IEEE website at\u00a0www.ieee.org. P. Blaise,1,2 “Ab Initio\u2026<\/div><\/div><\/article>
February 26, 2020<\/div>
Technical Libraries<\/div><\/div>

Solar Cells<\/a><\/h3>
Solar Cells<\/span>TCAD Published Papers<\/span><\/div>
Solar Cells The full text for most of these papers may be found at the IEEE website at\u00a0www.ieee.org. Samy Almosni,[a,b]\u00a0Ludmila Cojocaru,[a]\u00a0Debin Li,[c]\u00a0Satoshi\u2026<\/div><\/div><\/article>
February 26, 2020<\/div>
Technical Libraries<\/div><\/div>

MEMS<\/a><\/h3>
MEMS<\/span>TCAD Published Papers<\/span><\/div>
MEMS The full text for most of these papers may be found at the IEEE website at\u00a0www.ieee.org. Yonghyun Shim, Member, IEEE, Jean-Pierre\u2026<\/div><\/div><\/article>
February 26, 2020<\/div>
Technical Libraries<\/div><\/div>

Memory Devices<\/a><\/h3>
TCAD Published Papers<\/span><\/div>
Memory Devices The full text for most of these papers may be found at the IEEE website at\u00a0www.ieee.org. Daewoong Kang, Hyungcheol Shin,\u2026<\/div><\/div><\/article>
February 26, 2020<\/div>
Technical Libraries<\/div><\/div>

Optoelectronics<\/a><\/h3>
Optoelectronics<\/span>TCAD Published Papers<\/span><\/div>
Optoelectronics The full text for most of these papers may be found at the IEEE website at\u00a0www.ieee.org. H. Matsuura, S. Sakurai, Y.\u2026<\/div><\/div><\/article>
February 26, 2020<\/div>
Technical Libraries<\/div><\/div>

Radiation, SEU and Reliability<\/a><\/h3>
Radiation, SEU and Reliability<\/span>TCAD Published Papers<\/span><\/div>
Radiation, SEU and Reliability The full text for most of these papers may be found at the IEEE website at\u00a0www.ieee.org. Takashi Kameshima,\u2026<\/div><\/div><\/article>
February 26, 2020<\/div>
Technical Libraries<\/div><\/div>

Power Device Simulation<\/a><\/h3>
Power Devices Simulation<\/span>TCAD Published Papers<\/span><\/div>
Power Device Simulation The full text for most of these papers may be found at the IEEE website at\u00a0www.ieee.org. Viviana Cerantonio, Marcello\u2026<\/div><\/div><\/article>
February 26, 2020<\/div>
Technical Libraries<\/div><\/div>

ESD Simulation<\/a><\/h3>
ESD Simulation<\/span>TCAD Published Papers<\/span><\/div>
ESD Simulation The full text for most of these papers may be found at the IEEE website at\u00a0www.ieee.org. Guido Notermans, Olivier Quittard,\u2026<\/div><\/div><\/article>
February 26, 2020<\/div>
Technical Libraries<\/div><\/div>

Organic Device Technology<\/a><\/h3>
Organic Device Technology<\/span>TCAD Published Papers<\/span><\/div>
Organic Device Technology The full text for most of these papers may be found at the IEEE website at\u00a0www.ieee.org. Debin Li, “Recent\u2026<\/div><\/div><\/article>
February 26, 2020<\/div>
Technical Libraries<\/div><\/div>

Interconnect Simulation<\/a><\/h3>
Interconnect Simulation<\/span>TCAD Published Papers<\/span><\/div>
Interconnect Simulation The full text for most of these papers may be found at the IEEE website at\u00a0www.ieee.org. Keh-Jeng Chang, Jyh-Jeng Chou,\u2026<\/div><\/div><\/article>
February 26, 2020<\/div>
Technical Libraries<\/div><\/div>

SOI Technology<\/a><\/h3>
TCAD Published Papers<\/span><\/div>
SOI Technology The full text most of these papers may be found at the IEEE website at\u00a0www.ieee.org. Ali A. Orouji, Hamid Amini\u2026<\/div><\/div><\/article>
February 26, 2020<\/div>
Technical Libraries<\/div><\/div>

TFT Technology<\/a><\/h3>
TCAD Published Papers<\/span>TFT Technology<\/span><\/div>
TFT Technology The full text for most of these papers may be found at the IEEE website at\u00a0www.ieee.org. Yu-Shien Shiah1,\u00a0Kihyung Sim1, Yuhao\u2026<\/div><\/div><\/article>
February 26, 2020<\/div>
Technical Libraries<\/div><\/div>

Compound Devices<\/a><\/h3>
Compound Devices<\/span>TCAD Published Papers<\/span><\/div>
Compound Devices The full text for most of these papers may be found at the IEEE website at\u00a0www.ieee.org. N. Seoane1, M. Aldegunde1,\u2026<\/div><\/div><\/article>
February 26, 2020<\/div>
Technical Libraries<\/div><\/div>

CMOS Technology<\/a><\/h3>
CMOS Technology<\/span>TCAD Published Papers<\/span><\/div>
CMOS Technology The full text for most of these papers may be found at the IEEE website at\u00a0www.ieee.org. T Uchino1, 2,\u00a0E Gili1,\u2026<\/div><\/div><\/article>
February 26, 2020<\/div>
Technical Libraries<\/div><\/div>

Process Simulation<\/a><\/h3>
Process Simulation<\/span>TCAD Published Papers<\/span><\/div>
Process Simulation The full text for most of these papers may be found at the IEEE website at\u00a0www.ieee.org. Guriqbal Singh Josan, Archana\u2026<\/div><\/div><\/article>
February 24, 2020<\/div>
POST<\/div><\/div>

What’s in the New MIPI Alliance I3C V1.1 Standard?<\/a><\/h3>
SIPware Webinars<\/span><\/div>
February 27th 2020 | 10:00 am - 11:00 am (PST) I3C has the advantages in reducing pin count, increasing performance, and decreasing\u2026<\/div><\/div><\/article>
February 19, 2020<\/div>
News<\/div><\/div>

Weebit Nano and Silvaco Develop New Simulation Capabilities to Increase ReRAM Adoption<\/a><\/h3>
TCAD News<\/span>TCAD Press<\/span><\/div>
February 19, 2020<\/div><\/div><\/article>
February 6, 2020<\/div>
POST<\/div><\/div>

TCAD of Innovative Nanodevices with Victory Atomistic<\/a><\/h3>
TCAD Webinars<\/span><\/div>
TCAD of Innovative Nanodevices with Victory Atomistic This webinar will introduce to the simulation capabilities of Victory Atomistic (VA) as part of\u2026<\/div><\/div><\/article>
February 5, 2020<\/div>
News<\/div><\/div>

Two-dimensional oscillatory neural networks for energy efficient neuromorphic computing<\/a><\/h3>
TCAD News<\/span><\/div>
Feb. 5, 2020 On the 4 th and 5th of February 2020, in Montpellier (France), at the premises of LIRMM, CNRS the\u2026<\/div><\/div><\/article>
January 24, 2020<\/div>
POST<\/div><\/div>

New MIPI I3C V1.1 Standard Streamlines Peripheral Connectivity with Lower Cost and Higher Bandwidth<\/a><\/h3>
SIPware Blogs<\/span><\/div>
The MIPI Alliance (MIPI) develops interface specifications for mobile and mobile-influenced industries. There is at least one MIPI specification in every smartphone\u2026<\/div><\/div><\/article>
January 16, 2020<\/div>
Custom Webinars<\/div><\/div>

Accelerate the Circuit Simulation Flow with Jivaro Parasitic Reduction<\/a><\/h3>
Parasitics+Netlist Webinars<\/span>SPICE Webinars<\/span><\/div>
Accelerate the Circuit Simulation Flow with Jivaro Parasitic Reduction Jivaro is a unique, stand-alone solution for the reduction of parasitic networks that\u2026<\/div><\/div><\/article>
January 7, 2020<\/div>
POST<\/div><\/div>

For Next Generation Nanowires, Simulation from Atoms to SPICE<\/a><\/h3>
TCAD Blogs<\/span><\/div>
As process nodes continue to shrink, the requirement for additional physics-based simulation is gradually creeping into each stage of the design process.\u2026<\/div><\/div><\/article>
December 18, 2019<\/div>
POST<\/div><\/div>

Atomistic Analysis and Next Generation Computing at IEDM 2019<\/a><\/h3>
TCAD Blogs<\/span><\/div>
IEDM is THE device conference with more than a thousand participants from major companies and R&D institutes. Many talks were dedicated to\u2026<\/div><\/div><\/article>
December 14, 2019<\/div>
POST<\/div><\/div>

TCAD Recommended Textbooks<\/a><\/h3>
TCAD Textbooks<\/span><\/div>
CMOS: Mixed-Signal Circuit Design, Second Edition R. Jacob Baker. Published Wiley-IEEE Press, 2nd Edition. Published 2009, pp. 330 ISBN 978-0-470-29026-2 Understanding Modern\u2026<\/div><\/div><\/article>
December 12, 2019<\/div>
POST<\/div><\/div>

IP Solutions for Secure Autonomous Driving<\/a><\/h3>
SIPware Webinars<\/span><\/div>
IP Solutions for Secure Autonomous Driving This webinar will present the risks and necessary countermeasures for securing cyber-physical vehicle systems. Manufacturers are\u2026<\/div><\/div><\/article>
November 26, 2019<\/div>
POST<\/div><\/div>

Free 350 pg. Book on SoC Design and Secure Autonomous Driving Webinar<\/a><\/h3>
SIPware Blogs<\/span><\/div>
Silvaco has an upcoming webinar IP Solutions for Secure Autonomous Driving on Dec. 3, 10am \u2013 11am (PST) . The webinar will\u2026<\/div><\/div><\/article>
November 21, 2019<\/div>
POST<\/div><\/div>

Optimization of the Select Gate Transistor in a 3D NAND Memory Cell<\/a><\/h3>
TCAD Webinars<\/span><\/div>
Optimization of the Select Gate Transistor in a 3D NAND Memory Cell This webinar will present the usage of TCAD process and\u2026<\/div><\/div><\/article>
November 21, 2019<\/div>
Custom Blogs<\/div><\/div>

Customer Case Study: Using SmartSpice to Deliver Next-Generation, Low Power Memory Systems<\/a><\/h3>
At our SURGE Santa Clara event in October, Cameron Fisher, CEO of Mobile Semiconductor described their experience in adopting SmartSpice as their\u2026<\/div><\/div><\/article>
November 19, 2019<\/div>
POST<\/div><\/div>

Silvaco Exhibits and Presents Invited Paper on Atomistic Simulation at IEDM 2019<\/a><\/h3>
TCAD Blogs<\/span><\/div>
The IEEE International Electron Devices Meeting (IEDM) is the world\u2019s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and\u2026<\/div><\/div><\/article>
November 7, 2019<\/div>
POST<\/div><\/div>

Simulating Silicon Devices at Cryogenic Temperatures<\/a><\/h3>
TCAD Webinars<\/span><\/div>
Simulating Silicon Devices at Cryogenic Temperatures This webinar discusses the problems encountered when using the Drift-Diffusion method to simulate the behavior of\u2026<\/div><\/div><\/article>
October 31, 2019<\/div>
POST<\/div><\/div>

SiC and Other Wide Bandgap Materials: From Process to Device Simulation<\/a><\/h3>
TCAD Webinars<\/span><\/div>
This webinar provides an overview of Silvaco\u2019s TCAD tools. It introduces Silvaco\u2019s process and device simulation capabilities for wide bandgap materials. In\u2026<\/div><\/div><\/article>
October 25, 2019<\/div>
POST<\/div><\/div>

How TCAD Can Optimize Power Electronics<\/a><\/h3>
TCAD Blogs<\/span><\/div>
The power electronics (PE) market is growing rapidly, driven by the accelerating demand of EV and HEV vehicles. Power devices lend themselves\u2026<\/div><\/div><\/article>
October 24, 2019<\/div>
Custom Blogs<\/div><\/div>

SmartSpice Does It Smart<\/a><\/h3>
By this definition, any SPICE simulator qualifies as a smart design tool, but what about versatility? SmartSpice has had over 30 years\u2026<\/div><\/div><\/article>
October 24, 2019<\/div>
POST<\/div><\/div>

AI and Machine Learning SoCs \u2013 Memory and Interconnect IP Perspectives<\/a><\/h3>
SIPware Webinars<\/span><\/div>
AI and Machine Learning SoCs \u2013 Memory and Interconnect IP Perspectives This webinar will discuss the challenges of developing of artificial intelligence\u2026<\/div><\/div><\/article>
October 10, 2019<\/div>
Custom Webinars<\/div><\/div>

On-Chip Variation and the Sign-off Timing Flow: An Industry Perspective<\/a><\/h3>
Library Webinars<\/span><\/div>
As semiconductor technology advances, the impact of on-chip variation increases, which means more sophisticated solutions are required.<\/div><\/div><\/article>
October 1, 2019<\/div>
Simulation Standard<\/div><\/div>

Maverick: Hierarchical Netlist Extractor for PC Platforms<\/a><\/h3>
Diamond is considered to be the ultimate semiconductor material for high power and high frequency devices due to its superior electrical and\u2026<\/div><\/div><\/article>
September 18, 2019<\/div>
News<\/div><\/div>

MEDIA ALERT: Meet Silvaco at the TSMC OIP Ecosystem Forum<\/a><\/h3>
September 18, 2019<\/div><\/div><\/article>
September 16, 2019<\/div>
POST<\/div><\/div>

Silvaco Partners with HDL Design House for Analog and Digital IC Design Services<\/a><\/h3>
SPICE News<\/span><\/div>
September 16, 2019<\/div><\/div><\/article>
September 9, 2019<\/div>
POST<\/div><\/div>

The Need for Advanced Wide Bandgap Power Electronics<\/a><\/h3>
TCAD Blogs<\/span><\/div>
PowerAmerica\u2019s strategic roadmap for next generation wide bandgap (WBG) power electronics (PE) came out earlier this year. The public version of the\u2026<\/div><\/div><\/article>
September 5, 2019<\/div>
Simulation Standard<\/div><\/div>

Next Generation CMOS Nanowire: From Atoms to Circuit Simulation<\/a><\/h3>
Abstract\u2014 A complete simulation flow for a Nanowire-based ring oscillator circuit is presented, where the active devices were simulated using an atomistic\u2026<\/div><\/div><\/article>
September 4, 2019<\/div>
POST<\/div><\/div>

3D TCAD Simulation for Power Devices<\/a><\/h3>
TCAD Blogs<\/span><\/div>
y first IC design back in 1978 was a DRAM and it ran on 12V, 5V and -5V, but then my second\u2026<\/div><\/div><\/article>
September 4, 2019<\/div>
Simulation Standard<\/div><\/div>

Optimization of Select Gate Transistor in Advanced 3D NAND Memory Cell<\/a><\/h3>
Abstract\u2014There are several device challenges unique to the select gate transistor in 3D NAND memory cell. It requires low leakage current to\u2026<\/div><\/div><\/article>
September 3, 2019<\/div>
Simulation Standard<\/div><\/div>

RFSOI Switch Harmonics Simulations with Trap-Rich Substrate<\/a><\/h3>
In this paper, in order to understand trap-rich substrate behavior, passive and active device on SOI with trap-rich layer structures were simulated\u2026<\/div><\/div><\/article>
September 3, 2019<\/div>
Simulation Standard<\/div><\/div>

Estimation of Interface Property Changes Between Normally On\/Off Hydrogenated Diamond MISFETs<\/a><\/h3>
Introduction Diamond is considered to be the ultimate semiconductor material for high power and high frequency devices due to its superior electrical\u2026<\/div><\/div><\/article>
August 29, 2019<\/div>
POST<\/div><\/div>

Where Circuit Simulation Model Files Come From<\/a><\/h3>
TCAD Blogs<\/span><\/div>
I started out my engineering career by doing transistor-level circuit design and we used a proprietary SPICE circuit simulator. One thing that\u2026<\/div><\/div><\/article>
August 16, 2019<\/div>
POST<\/div><\/div>

230 Papers on Power Device Simulations using Silvaco TCAD<\/a><\/h3>
TCAD Blogs<\/span><\/div>
A quick search of the IEEE Xplore online library gives a list of more than 230 published technical articles on Power Device\u2026<\/div><\/div><\/article>
August 15, 2019<\/div>
Custom Webinars<\/div><\/div>

Fast Capacitance Extraction Within the Expert Layout Editor Using Hipex and the Stellar Solver for a Touch Panel Application<\/a><\/h3>
Fast Capacitance Extraction Within the Expert Layout Editor Using Hipex and the Stellar Solver for a Touch Panel Application The Stellar GUI-based\u2026<\/div><\/div><\/article>
August 15, 2019<\/div>
POST<\/div><\/div>

Advanced Materials and New Architectures for AI Applications<\/a><\/h3>
TCAD Blogs<\/span><\/div>
Over the past 50 years in our industry, there have been three invariant principles: Moore\u2019s Law drives the pace of Si technology\u2026<\/div><\/div><\/article>
August 9, 2019<\/div>
POST<\/div><\/div>

Everything You Want to Know about Silvaco Foundation IP<\/a><\/h3>
SIPware Blogs<\/span><\/div>
In the creation of an ASIC or SoC a wide variety of digital components are needed. Standard logic cells are used to\u2026<\/div><\/div><\/article>
August 1, 2019<\/div>
News<\/div><\/div>

Silvaco Appoints Babak Taheri as new Chief Executive Officer<\/a><\/h3>
August 1, 2019<\/div><\/div><\/article>
July 26, 2019<\/div>
POST<\/div><\/div>

System and Method for IP Fingerprinting and IP DNA Analysis<\/a><\/h3>
SIPware Blogs<\/span><\/div>
In the world of SoC development, an IP management system is software for the licensing, distribution and compliance administration of design IP\u2026<\/div><\/div><\/article>
July 23, 2019<\/div>
News<\/div><\/div>

Silvaco Partners with Incubator Silicon Power Technology to Accelerate Success of Semiconductor Startups<\/a><\/h3>
July 23, 2019<\/div><\/div><\/article>
July 18, 2019<\/div>
Custom Blogs<\/div><\/div>

Machine Learning in Silvaco EDA Software<\/a><\/h3>
In the following video, Dr. Firas Mohamed, VP & GM, Machine Learning & Flow Optimization Division and GM, Silvaco France talks with\u2026<\/div><\/div><\/article>
July 17, 2019<\/div>
Custom News<\/div><\/div>

Pioneer Micro Technology Launches Silvaco PDK for its 0.35 \u00b5m Silicon Foundry CMOS Process<\/a><\/h3>
July 17, 2019<\/div><\/div><\/article>
July 11, 2019<\/div>
POST<\/div><\/div>

Silvaco SIPware Automotive IP<\/a><\/h3>
SIPware Webinars<\/span><\/div>
Silvaco SIPware Automotive IP Silvaco has partnered with semiconductor leaders like NXP, Infineon and TI to offer a comprehensive portfolio of automotive\u2026<\/div><\/div><\/article>
July 11, 2019<\/div>
POST<\/div><\/div>

I\/O Design and Characterization \u2013 How Can You Compete with Free?<\/a><\/h3>
SIPware Blogs<\/span><\/div>
I interviewed Silvaco partner Stephen Fairbanks, CTO of Certus Semiconductor from the show floor at DAC 2019, in Las Vegas, about I\/O\u2026<\/div><\/div><\/article>
July 5, 2019<\/div>
Simulation Standard<\/div><\/div>

TCAD Simulation of Electric Field Distribution in Gallium Nitride Trench-based Power Devices<\/a><\/h3>
Introduction Gallium nitride (GaN)-based devices are excellent candidates for high-voltage and high-power applications, due to the superior physical properties of GaN compared\u2026<\/div><\/div><\/article>
July 4, 2019<\/div>
Simulation Standard<\/div><\/div>

Channel-length Dependence of a-IGZO TFTs with Self-heating Effects<\/a><\/h3>
Introduction Amorphous In-Ga-Zn-O thin-film transistors (a-IGZO TFTs) show a high mobility, a small sub-threshold swing, and a low OFF-current, and they are\u2026<\/div><\/div><\/article>
July 3, 2019<\/div>
Simulation Standard<\/div><\/div>

Simulation of Different Tunnel Junctions in InGaP\/GaAs, InGaP\/CdTe Dual Junction Solar Cells<\/a><\/h3>
Abstract \u2014 Dual junction solar cells were simulated using Silvaco TCAD tool with various tunnel junction material compositions. InGaP\/GaAs dual junction solar\u2026<\/div><\/div><\/article>
July 2, 2019<\/div>
POST<\/div><\/div>

Talking Atoms to Systems in Next-Generation SoC Designs<\/a><\/h3>
TCAD Blogs<\/span><\/div>
New system-on-chip (SoC) devices are driving new memory architectures and photonic interfaces, while specialized new intellectual property (IP) requires analysis down to\u2026<\/div><\/div><\/article>
July 1, 2019<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips and Solutions – July, August, September 2019<\/a><\/h3>
Q. Is it possible to emulate a deep reactive ion etch process (e.g. deep trench with scalloped sidewalls) without using a physical\u2026<\/div><\/div><\/article>
June 25, 2019<\/div>
POST<\/div><\/div>

Robust SPICE Modeling with Verilog-A: Principles and Practical Techniques<\/a><\/h3>
Modeling Webinars<\/span>SPICE Webinars<\/span><\/div>
Robust SPICE Modeling with Verilog-A: Principles and Practical Techniques Insufficient robustness of models in SPICE circuit simulators may lead to a poor\u2026<\/div><\/div><\/article>
June 25, 2019<\/div>
Custom Blogs<\/div><\/div>

5nm Success \u2013 Silicon Creations CEO Video Interview at DAC 2019<\/a><\/h3>
In the following video, I interview Silvaco customer Randy Caplan of Silicon Creations from the show floor at DAC 2019, in Las\u2026<\/div><\/div><\/article>
June 24, 2019<\/div>
Webinars for Display Week<\/div><\/div>

Simulation and Analysis of Liquid Crystal on Silicon Pixels for Augmented Reality and Holography Applications<\/a><\/h3>
TCAD Webinars<\/span><\/div>
July 24, 2019 Since its invention in the early 1970s, liquid crystal on silicon (LCoS) technology has proven its success in a\u2026<\/div><\/div><\/article>
June 18, 2019<\/div>
POST<\/div><\/div>

Design Flow Applications Using the SmartSpice Analysis Engine<\/a><\/h3>
SPICE Webinars<\/span><\/div>
Design Flow Applications Using the SmartSpice Analysis Engine Circuit Simulation is at the heart of many Board, IC and Package design flows.\u2026<\/div><\/div><\/article>
June 7, 2019<\/div>
POST<\/div><\/div>

Launching Samsung Foundry IP as Silvaco IP \u2013 What you Need to Know<\/a><\/h3>
SIPware Blogs<\/span><\/div>
On Monday, May 13, Silvaco announced that the semiconductor design IP of Samsung Foundry is now marketed, licensed and supported through Silvaco.\u2026<\/div><\/div><\/article>
June 3, 2019<\/div>
POST<\/div><\/div>

CEA-Leti and Silvaco Team Up on Yield-Prediction Project For Ultra-Low-Power Static Memories<\/a><\/h3>
Variation News<\/span><\/div>
June 3, 2019<\/div><\/div><\/article>
May 30, 2019<\/div>
POST<\/div><\/div>

Silvaco and Si2 Release Unique, Free 15nm Open-Source Digital Cell Library<\/a><\/h3>
Foundation IP News<\/span><\/div>
Silvaco and Si2 Release Unique, Free 15nm Open-Source Digital Cell Library Silvaco Contribution to Si2 Will Improve Innovation in State-of-the Art Nanometer\u2026<\/div><\/div><\/article>
May 28, 2019<\/div>
TCAD Training<\/div><\/div>

Silvaco TCAD: Introduction and the Basics – A Tutorial in 3 Parts<\/a><\/h3>
TCAD Webinars<\/span><\/div>
In this 3-part webinar series, viewers will be introduced to the suite of Silvaco TCAD software, and offered starter training and tutorial.\u2026<\/div><\/div><\/article>
May 28, 2019<\/div>
POST<\/div><\/div>

Silvaco Announces Viola 10X \u2013 An Order of Magnitude Faster Characterization for Nanometer Silicon<\/a><\/h3>
Library News<\/span><\/div>
May 28, 2019<\/div><\/div><\/article>
May 28, 2019<\/div>
TCAD Training<\/div><\/div>

Silvaco TCAD: Introduction and the Basics – Part 3<\/a><\/h3>
TCAD Webinars<\/span><\/div>
Silvaco TCAD: Introduction and the Basics – A Tutorial in 3 Parts Part III-TCAD Process Simulation Silvaco TCAD can be applied to\u2026<\/div><\/div><\/article>
May 23, 2019<\/div>
POST<\/div><\/div>

Inventing the Future of MicroLED: Silvaco TCAD<\/a><\/h3>
TCAD Blogs<\/span><\/div>
Silvaco did Executive Video Interviews at our booth in the middle of the show floor at Display Week 2019 in San Jose.\u2026<\/div><\/div><\/article>
May 22, 2019<\/div>
Webinars for Display Week<\/div><\/div>

Device Simulation of Oxide Semiconductor TFTs: Device Modeling and Self-Heating Effects<\/a><\/h3>
TCAD Webinars<\/span><\/div>
May 22, 2018 This webinar shows how to use Silvaco simulators for OS TFT device simulation. The carrier-electron transport and electronic states\u2026<\/div><\/div><\/article>
May 21, 2019<\/div>
News<\/div><\/div>

Stars of IP Party Tees Off in Las Vegas<\/a><\/h3>
May 21, 2019<\/div><\/div><\/article>
May 21, 2019<\/div>
TCAD Training<\/div><\/div>

Silvaco TCAD: Introduction and the Basics – Part 2<\/a><\/h3>
TCAD Webinars<\/span><\/div>
Part II of this webinar series takes a dive into creating a new device simulation deck. Attendees will learn how to use\u2026<\/div><\/div><\/article>
May 21, 2019<\/div>
News<\/div><\/div>

Silvaco Announces Worldwide SURGE Schedule for 2019<\/a><\/h3>
May 21, 2019<\/div><\/div><\/article>
May 20, 2019<\/div>
Custom News<\/div><\/div>

ClioSoft and Silvaco Collaborate to Integrate ClioSoft\u2019s SOS Design Data Management Platform with Silvaco\u2019s Analog Custom Design Tools<\/a><\/h3>
May 20, 2019<\/div><\/div><\/article>
May 19, 2019<\/div>
POST<\/div><\/div>

Samsung Foundry and Silvaco Begin Partnership to Launch Samsung Foundry Semiconductor IP<\/a><\/h3>
SIPware Blogs<\/span><\/div>
On Monday, May 13, Silvaco announced that the semiconductor design IP of Samsung Foundry is now marketed, licensed and supported through Silvaco.\u2026<\/div><\/div><\/article>
May 13, 2019<\/div>
POST<\/div><\/div>

Samsung Foundry Begins Partnership with Silvaco to Launch their Semiconductor IP Assets<\/a><\/h3>
Foundation IP News<\/span><\/div>
Samsung Foundry Begins Partnership with Silvaco to Launch their Semiconductor IP Assets Santa Clara, CA – May 13, 2019\u00a0– Silvaco Inc., a\u2026<\/div><\/div><\/article>
May 13, 2019<\/div>
News<\/div><\/div>

Silvaco Presents Smart Solutions from Atoms to Systems at DAC 2019<\/a><\/h3>
May 13, 2019<\/div><\/div><\/article>
May 10, 2019<\/div>
POST<\/div><\/div>

New Whitepaper: Comprehensive Design Solutions for Display Technology<\/a><\/h3>
TCAD Blogs<\/span><\/div>
Silvaco has a large booth in the middle of the show floor at Display Week 2019 at the San Jose Convention Center,\u2026<\/div><\/div><\/article>
May 7, 2019<\/div>
TCAD Training<\/div><\/div>

Silvaco TCAD: Introduction and the Basics – Part 1<\/a><\/h3>
TCAD Webinars<\/span><\/div>
Silvaco TCAD: Introduction and the Basics – A Tutorial in 3 Parts Part I – Overview of Silvaco TCAD Silvaco TCAD can\u2026<\/div><\/div><\/article>
May 2, 2019<\/div>
Custom Webinars<\/div><\/div>

Accelerate Custom Layout Editing with Expert and JavaScript<\/a><\/h3>
Accelerate Custom Layout Editing with Expert and JavaScript Expert is a powerful hierarchical layout editor suitable for a wide variety of design\u2026<\/div><\/div><\/article>
April 30, 2019<\/div>
POST<\/div><\/div>

Managing Design Technology Co-Optimization (DTCO) Using One Command File<\/a><\/h3>
TCAD Webinars<\/span><\/div>
Managing Design Technology Co-Optimization (DTCO) Using One Command File This webinar illustrates the advantages of using a single command file and a\u2026<\/div><\/div><\/article>
April 26, 2019<\/div>
POST<\/div><\/div>

Modeling Quantum Dot Based hyLEDs using Radiant<\/a><\/h3>
TCAD Blogs<\/span><\/div>
Radiant is a graphical user interface (GUI) for TCAD simulations which lowers the entry barrier for inexperienced users to doing technology analysis.\u2026<\/div><\/div><\/article>
April 24, 2019<\/div>
POST<\/div><\/div>

Unraveling and Optimizing Transistor-Level Simulation<\/a><\/h3>
SPICE Webinars<\/span><\/div>
Unraveling and Optimizing Transistor-Level Simulation Circuit Simulation is one of the most critical parts of the design process. Validating circuit behavior is\u2026<\/div><\/div><\/article>
April 23, 2019<\/div>
News<\/div><\/div>

Silvaco Opens Chengdu Office to Support Company\u2019s China Expansion and Growing Demand for Power Semiconductor Design Solutions<\/a><\/h3>
April 23, 2019<\/div><\/div><\/article>
April 23, 2019<\/div>
POST<\/div><\/div>

Next Generation of SoC Design: From Atoms to Systems<\/a><\/h3>
SIPware Webinars<\/span><\/div>
Next Generation of SoC Design: From Atoms to Systems This webinar provides examples of how complex new technologies such as Flash memory,\u2026<\/div><\/div><\/article>
April 19, 2019<\/div>
POST<\/div><\/div>

Design IP for Automotive SoCs: Trends and Solutions<\/a><\/h3>
SIPware Blogs<\/span><\/div>
The number and complexity of automotive SoCs and Control Systems is growing dramatically to fill the demand for new features in next-generation\u2026<\/div><\/div><\/article>
April 16, 2019<\/div>
News<\/div><\/div>

Silvaco Joins SEMI, and Electronic System Design Alliance, a SEMI Strategic Association Partner<\/a><\/h3>
April 16, 2019<\/div><\/div><\/article>
April 6, 2019<\/div>
Custom Blogs<\/div><\/div>

Six-Sigma Analysis of Digital Standard Cells<\/a><\/h3>
library of digital standard cells implements both Boolean logic and sequential storage functions. These foundation IPs are used extensively and repeatedly within\u2026<\/div><\/div><\/article>
April 4, 2019<\/div>
TCAD Training<\/div><\/div>

Introduction to Atomistic Simulation for Nanodevices<\/a><\/h3>
TCAD Webinars<\/span><\/div>
Introduction to Atomistic Simulation for Nanodevices This webinar will provide introduction to the atomistic simulation capabilities of NEMO5, which is evolving into\u2026<\/div><\/div><\/article>
April 1, 2019<\/div>
Simulation Standard<\/div><\/div>

Process Simulation \u2013 New Features in 2019 Baseline Release<\/a><\/h3>
2019 baseline release of Victory Process includes improvements and extensions to the following modules: Physical etching\/deposition Stress simulation Annealing\/oxidation<\/div><\/div><\/article>
April 1, 2019<\/div>
Simulation Standard<\/div><\/div>

Meshing \u2013 New Features in 2019 Baseline Release<\/a><\/h3>
The 2019 TCAD baseline release of Victory Mesh now contains Solid Modeling functionality. The term Solid Modeling is used to refer to\u2026<\/div><\/div><\/article>
April 1, 2019<\/div>
Simulation Standard<\/div><\/div>

Device Simulation \u2013 New Features in 2019 Baseline Release<\/a><\/h3>
The effect of Coulomb interaction in the absorption spectrum of quantum wells (QWs) is responsible for the quantum confined Stark effect (QCSE),\u2026<\/div><\/div><\/article>
April 1, 2019<\/div>
Simulation Standard<\/div><\/div>

Interactive Tools – New Features in 2019 Baseline Release<\/a><\/h3>
DeckBuild is Silvaco\u2019s state of the art simulator interface. It is capable of running all simulators from Silvaco as well as many\u2026<\/div><\/div><\/article>
April 1, 2019<\/div>
Technical Libraries<\/div><\/div>

Bipolar Technology<\/a><\/h3>
Bipolar Technology<\/span>TCAD Published Papers<\/span><\/div>
Bipolar Technology The full text for most of these papers may be found at the IEEE website at\u00a0www.ieee.org. A. S. Zoolfakar, N.\u2026<\/div><\/div><\/article>
March 26, 2019<\/div>
POST<\/div><\/div>

TCAD-based Model Extraction Flow for GaN HEMT Devices – Part 2<\/a><\/h3>
Modeling Webinars<\/span>TCAD Webinars<\/span><\/div>
TCAD-based Model Extraction Flow for GaN HEMT Devices – Part 2 This webinar represents a continuation of a previously presented parameter extraction\u2026<\/div><\/div><\/article>
March 22, 2019<\/div>
POST<\/div><\/div>

Remembering Dr. Misha Temkin, Aug. 1955 \u2013 Mar. 2019<\/a><\/h3>
TCAD Blogs<\/span><\/div>
Dr. Misha Temkin was a beloved colleague and researcher who worked at Silvaco for over 30 years. He passed on March 12,\u2026<\/div><\/div><\/article>
March 21, 2019<\/div>
POST<\/div><\/div>

Challenges and Solutions of Nanometer Library Characterization<\/a><\/h3>
Library Blogs<\/span>SIPware Blogs<\/span><\/div>
Graham Bell sits down with Bernardo Culau, Director of Characterization, to discuss the challenges and Solutions of Nanometer Library Characterization. They also\u2026<\/div><\/div><\/article>
March 21, 2019<\/div>
POST<\/div><\/div>

Nanometer Library Characterization: Challenges and Solutions<\/a><\/h3>
Library Webinars<\/span>SIPware Webinars<\/span><\/div>
Nanometer Library Characterization: Challenges and Solutions Designers today see a significant increase in the number of simulations and PVT corners required to\u2026<\/div><\/div><\/article>
March 15, 2019<\/div>
POST<\/div><\/div>

Chris Browy of Avery Design Sits Down to Discuss Why Silvaco and Avery are Working Together<\/a><\/h3>
SIPware Blogs<\/span><\/div>
Silvaco just announced an agreement with Avery Designs for the distribution of Avery\u2019s verification IP (VIP) for the MIPI I3C sensor interface\u2026<\/div><\/div><\/article>
February 28, 2019<\/div>
POST<\/div><\/div>

Simulation of Reliability and NBTI Aging in MOS Microelectronics<\/a><\/h3>
TCAD Webinars<\/span><\/div>
Simulation of Reliability and NBTI Aging in MOS Microelectronics The continuous scaling of semiconductor devices is a driving force in the field\u2026<\/div><\/div><\/article>
February 26, 2019<\/div>
News<\/div><\/div>

Silvaco Opens Shenzhen Office to Support Company\u2019s Asian Expansion and Growing Demand for Semiconductor Design Solutions<\/a><\/h3>
February 26, 2019<\/div><\/div><\/article>
February 25, 2019<\/div>
POST<\/div><\/div>

Silvaco, Inc. and Avery Design Systems Partner to Deliver Complete CAN-FD Automotive and MIPI I3C IP and VIP Solutions<\/a><\/h3>
Foundation IP News<\/span><\/div>
Silvaco, Inc. and Avery Design Systems Partner to Deliver Complete CAN-FD Automotive and MIPI I3C IP and VIP Solutions TEWKSBURY, MA. and\u2026<\/div><\/div><\/article>
January 28, 2019<\/div>
Custom News<\/div><\/div>

Silicon Creations Relies on Silvaco’s Custom Design Flow for New Advanced FinFET Designs<\/a><\/h3>
January 28, 2019<\/div><\/div><\/article>
January 15, 2019<\/div>
Webinars for Display Week<\/div><\/div>

TCAD Solution for Flexible Display<\/a><\/h3>
TCAD Webinars<\/span><\/div>
January 15, 2018 In this webinar, we review the basic elements of device design for flexible displays, including the key factors affecting\u2026<\/div><\/div><\/article>
January 1, 2019<\/div>
Simulation Standard<\/div><\/div>

3D TFT Simulation of Grains and Grain Boundaries<\/a><\/h3>
Introduction Low-temperature polycrystalline silicon (LTPS) thin-film transistors have been widely applied to AMOLED (Active Matrix Organic Light Emitting Diode) as the most\u2026<\/div><\/div><\/article>
January 1, 2019<\/div>
Simulation Standard<\/div><\/div>

Quantum Dot-Based Hybrid Light Emitting Diode Modelling Using Radiant<\/a><\/h3>
Introduction With the recently launched Radiant, a graphical user interface (GUI) for Atlas-based TCAD simulations, the entry barrier for inexperienced users has\u2026<\/div><\/div><\/article>
January 1, 2019<\/div>
Simulation Standard<\/div><\/div>

Verification of an Compact Model for Organic Thin-Film-Transistors by Using MixedMode Creating an CMOS Inverter Circuit with TCAD Transistor Devices<\/a><\/h3>
Organic thin-film transistors (OTFTs) are promising devices for future low-cost electronics[1][2]. However, to enable the development of this technology, circuit design simulation\u2026<\/div><\/div><\/article>
January 1, 2019<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips and Solutions – Movie and PDF Report Generation with the DeckBuild GUI<\/a><\/h3>
Introduction In this article we will emphasize two new features of the DeckBuild deck editing environment. These are the movie creation on\u2026<\/div><\/div><\/article>
December 18, 2018<\/div>
Custom Blogs<\/div><\/div>

SPICE Model Generation by Machine Learning<\/a><\/h3>
by Thomas Blaesi It was 1988 when I got into SPICE (Simulation Program with Integrated Circuit Emphasis) while I was characterizing a\u2026<\/div><\/div><\/article>
December 18, 2018<\/div>
POST<\/div><\/div>

Improving Memory on the Edge Using Octal Serial Flash Cache<\/a><\/h3>
SIPware Webinars<\/span><\/div>
Improving Memory on the Edge Using Octal Serial Flash Cache This webinar will discuss the various solutions for storing and executing microprocessor\u2026<\/div><\/div><\/article>
December 11, 2018<\/div>
POST<\/div><\/div>

Bandstructure Effects in Nano Devices<\/a><\/h3>
TCAD Webinars<\/span><\/div>
Bandstructure Effects in Nano Devices&Examples Using NEMO5 As semiconductor device and circuit engineers we traditionally think of band edges and effective masses\u2026<\/div><\/div><\/article>
December 6, 2018<\/div>
POST<\/div><\/div>

SPICE Modeling for Flexible Electronics<\/a><\/h3>
Modeling Webinars<\/span>TCAD Webinars<\/span><\/div>
SPICE Modeling for Flexible Electronics Flexible electronics has an exciting potential for enabling bendable, rollable and foldable displays, smart product labeling as\u2026<\/div><\/div><\/article>
November 29, 2018<\/div>
POST<\/div><\/div>

MIPI I3C<\/a><\/h3>
SIPware Webinars<\/span><\/div>
MIPI I3C LEARN ABOUT MIPI I3C ALLIANCE STANDARD This webinar will provide a discussion of a new a standard from the MIPI\u2026<\/div><\/div><\/article>
October 1, 2018<\/div>
Simulation Standard<\/div><\/div>

Process Variation, Alignment and BEOL Effects on Circuit Level Performance<\/a><\/h3>
As process nodes continue to shrink, the requirement for additional physics is gradually creeping into each stage of the design process. By\u2026<\/div><\/div><\/article>
October 1, 2018<\/div>
Simulation Standard<\/div><\/div>

Touch Panel Capacitance Extraction in Hipex Full Chip Extraction Tool Using Stellar Field Solver<\/a><\/h3>
The previously standalone Stellar GUI based field solver tool for parasitic extraction is now integrated into Hipex (Silvaco\u2019s full chip extraction tool)\u2026<\/div><\/div><\/article>
October 1, 2018<\/div>
Simulation Standard<\/div><\/div>

Dynamic Analysis of Liquid Crystal Pixels<\/a><\/h3>
We have demonstrated in previous articles the static electrical and optical simulation of LC cells [1][2]. The last piece of the function\u2026<\/div><\/div><\/article>
October 1, 2018<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips and Solutions – Adding An Impurity to a Diffusion Model and Enable Diffusion of a New Impurity in a Specific Material<\/a><\/h3>
OBJECTIVE Add an impurity (H) to a material (silicon) for a diffusion model (Fermi). The description below refers to Victory Process version\u2026<\/div><\/div><\/article>
September 20, 2018<\/div>
POST<\/div><\/div>

Memory Statistical Characterization Solution with VarMan<\/a><\/h3>
Variation Webinars<\/span><\/div>
Memory Statistical Characterization Solution with VarMan With each new semiconductor process node, process variation, both global and local, play an increasingly significant\u2026<\/div><\/div><\/article>
August 21, 2018<\/div>
POST<\/div><\/div>

How FPD Designers Can Improve Productivity<\/a><\/h3>
TCAD Webinars<\/span><\/div>
This webinar will provide a discussion about new features of Silvaco\u2019s Layout Editor tool (Expert) for improving design productivity on FPD layout.<\/div><\/div><\/article>
July 19, 2018<\/div>
POST<\/div><\/div>

TCAD-based Model Extraction Flow for GaN HEMT Devices – Part 1<\/a><\/h3>
Modeling Webinars<\/span>TCAD Webinars<\/span><\/div>
TCAD-based Model Extraction Flow for GaN HEMT Devices This webinar will present a model parameter extraction methodology for GaN HEMT devices. This\u2026<\/div><\/div><\/article>
July 12, 2018<\/div>
Custom Webinars<\/div><\/div>

Standard Cell Layout Migration and Optimization<\/a><\/h3>
Library Webinars<\/span><\/div>
Standard Cell Layout Migration and Optimization This webinar will present an efficient methodology for migrating and optimizing standard cell libraries. Foundation IP\u2026<\/div><\/div><\/article>
July 1, 2018<\/div>
Simulation Standard<\/div><\/div>

3D Topography Simulation of SiC Epitaxial Growth Modeled by Diffusive Flux and Gibbs-Thomson Effect<\/a><\/h3>
One of wide bandgap semiconductors, SiC has been widely applied to the power devices, and then, the super-junction MOS transistor of SiC\u2026<\/div><\/div><\/article>
July 1, 2018<\/div>
Simulation Standard<\/div><\/div>

An Empirical Composition Dependent Model of Dopant Diffusion Coefficients in Si, Si1-x Gex and Ge Material Systems<\/a><\/h3>
Previously published fast empirical models for diffusion coefficients in silicon-germanium (Si1-x Gex) [1][2] were not applicable to high germanium content x\u22650.5 and\u2026<\/div><\/div><\/article>
July 1, 2018<\/div>
Simulation Standard<\/div><\/div>

TCAD Simulation of Leakage Through Threading Dislocations in GaN-based pn-diodes<\/a><\/h3>
Gallium nitride (GaN)-based devices for power electronics show superior performance in comparison to silicon carbide and silicon-based devices [1]\u2013[3]. The development of\u2026<\/div><\/div><\/article>
July 1, 2018<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips and Solutions – DeckBuild Remote VM Setup<\/a><\/h3>
This document describes how to setup a virtual environment suitable for the deckbuild remote mode. The host system to consider shall be\u2026<\/div><\/div><\/article>
June 21, 2018<\/div>
TCAD Training<\/div><\/div>

Introduction to TCAD \u2013 Device Theory Put into Practice<\/a><\/h3>
TCAD Webinars<\/span><\/div>
Introduction to TCAD \u2013 Device Theory Put into Practice TCAD process and device simulation is a powerful 2D and 3D modeling tool\u2026<\/div><\/div><\/article>
June 19, 2018<\/div>
Custom Webinars<\/div><\/div>

Exploration and Comparison of Various Parasitic Solutions and Parasitic-centric Calculations<\/a><\/h3>
Exploration and comparison of various parasitic solutions and parasitic-centric calculations This webinar will provide an overview on methods and tools to review\u2026<\/div><\/div><\/article>
June 14, 2018<\/div>
POST<\/div><\/div>

Bringing IP Management to the Enterprise Level<\/a><\/h3>
SIPware Webinars<\/span><\/div>
Bringing IP Management to the Enterprise Level IP reuse is no longer a new thing\u2014it is the lifeblood of any semiconductor company,\u2026<\/div><\/div><\/article>
May 17, 2018<\/div>
POST<\/div><\/div>

How TCAD Can Help You to Find The Right Material To Build Your Flexible Display<\/a><\/h3>
TCAD Webinars<\/span><\/div>
How TCAD Can Help You to Find The Right Material To Build Your Flexible Display The mechanical stress in a thin-film transistor\u2026<\/div><\/div><\/article>
April 12, 2018<\/div>
POST<\/div><\/div>

Subsystem Insight<\/a><\/h3>
SIPware Webinars<\/span><\/div>
Subsystem Insight Debugging Silvaco Subsystems with IAR Embedded Workbench Silvaco and IAR Systems have teamed up to provide software solutions for Silvaco\u2019s\u2026<\/div><\/div><\/article>
April 1, 2018<\/div>
Simulation Standard<\/div><\/div>

TCAD Simulation of Si and GaAs p-n Junction Devices at Cryogenic Temperatures, Down to 2 K<\/a><\/h3>
Cryogenic electronics plays a fundamental role in several applications, such as spacecraft, high-energy physics experiments, metrology, superconductive astronomical detectors and, with the\u2026<\/div><\/div><\/article>
April 1, 2018<\/div>
Simulation Standard<\/div><\/div>

Bi-axial Deformation with Victory Mesh for Flexible Electronic Applications<\/a><\/h3>
For high performance large area flexible electronics, amorphous metal oxide semiconductor based thin film transistors offer many advantages. These include high mobility,\u2026<\/div><\/div><\/article>
April 1, 2018<\/div>
Simulation Standard<\/div><\/div>

TCAD-based GaN HEMT Scalable Modeling Flow Using the MVSG Compact Model<\/a><\/h3>
Gallium Nitride High Electron Mobility (GaN HEMT) device technology has gained a lot of traction during the last years. These devices have\u2026<\/div><\/div><\/article>
April 1, 2018<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips and Solutions – Adding Random Noise to Mask Layout<\/a><\/h3>
Geometrical module of Victory Process allows the fast and accurate transfer of mask patterns to the structure. However, sometimes it is necessary\u2026<\/div><\/div><\/article>
March 29, 2018<\/div>
POST<\/div><\/div>

Accurate Parasitic RC Extraction using Realistic 3D TCAD Structures<\/a><\/h3>
TCAD Webinars<\/span><\/div>
Accurate Parasitic RC Extraction using Realistic 3D TCAD Structures Accurate determination of RC parasitics is a key component in the design and\u2026<\/div><\/div><\/article>
February 28, 2018<\/div>
POST<\/div><\/div>

Standard Cell Statistical Characterization with VarMan<\/a><\/h3>
Variation Webinars<\/span><\/div>
Standard Cell Statistical Characterization with VarMan With each new semiconductor process node, process variation, both global and local, play an increasingly significant\u2026<\/div><\/div><\/article>
February 18, 2018<\/div>
POST<\/div><\/div>

SPI vs SPI<\/a><\/h3>
SIPware Webinars<\/span><\/div>
SPI vs SPI This webinar will provide a discussion of Silvaco\u2019s SPI, QSPI, and OSPI IP products and how they are useful\u2026<\/div><\/div><\/article>
January 1, 2018<\/div>
Simulation Standard<\/div><\/div>

Advanced Process and Device 3D TCAD Simulation of Split-Gate Trench UMOSFET<\/a><\/h3>
Lower conduction loss and fast switching characteristics for power devices are increasingly required in the more and more energy-conscious world. For the\u2026<\/div><\/div><\/article>
January 1, 2018<\/div>
Simulation Standard<\/div><\/div>

Using TCAD to Reverse Engineer a 2N2222 BJT for Proton Damage Simulations<\/a><\/h3>
It is often the case, that an Engineer is required to simulate environmental effects on a device manufactured by a third party.\u00a0\u2026<\/div><\/div><\/article>
January 1, 2018<\/div>
Simulation Standard<\/div><\/div>

Optimization of PD-SOI CMOS Process and Devices for RF Applications<\/a><\/h3>
In recent years, radio-frequency (RF) CMOS on Silicon-on-Insulator (SOI) has rapidly evolved as a mainstream technology for switches used in wireless applications\u2026<\/div><\/div><\/article>
December 7, 2017<\/div>
Custom Webinars<\/div><\/div>

iPDK integration into Gateway Schematic Capture<\/a><\/h3>
iPDK integration into Gateway Schematic Capture This webinar will provide a discussion of the integration of iPDK design kits into the Gateway\u2026<\/div><\/div><\/article>
October 25, 2017<\/div>
POST<\/div><\/div>

TCAD Simulation of Ion Transport and Electrochemistry<\/a><\/h3>
TCAD Webinars<\/span><\/div>
TCAD Simulation of Ion Transport and Electrochemistry This webinar will discuss the simulation of ion transport and electrochemistry in semiconductor devices. These\u2026<\/div><\/div><\/article>
October 1, 2017<\/div>
Simulation Standard<\/div><\/div>

W-element Field Solvers<\/a><\/h3>
In connection with the reduction in the size of electronic elements and the increase in operating frequencies, it becomes necessary to transmit\u2026<\/div><\/div><\/article>
October 1, 2017<\/div>
Simulation Standard<\/div><\/div>

SmartSpice Shared Mode API<\/a><\/h3>
SmartSpice API, shared mode, was developed in order to provide an easy to use solution for products requiring the analog SPICE core\u2026<\/div><\/div><\/article>
October 1, 2017<\/div>
Simulation Standard<\/div><\/div>

Temperature Properties of Amorphous In-Ga-Zn-O Thin-Film Transistors with a new Mobility Model<\/a><\/h3>
Amorphous In-Ga-Zn-O (a-IGZO), which is a typical amorphous oxide conductor (AOS), is considered to be one of the most promising channel materials\u2026<\/div><\/div><\/article>
October 1, 2017<\/div>
Simulation Standard<\/div><\/div>

Automated Stress Simulation Interface Between Victory Process and Device<\/a><\/h3>
Victory Process now includes the Victory Stress library directly within the process simulator, which removes the necessity to keep switching from process\u2026<\/div><\/div><\/article>
October 1, 2017<\/div>
Simulation Standard<\/div><\/div>

TCAD Simulation of GaN-based Vertical FETs (HEMTs)<\/a><\/h3>
Gallium nitride (GaN)-based devices have entered the power electronics market and are showing excellent progress in the medium power conversion application [1]-[5].\u2026<\/div><\/div><\/article>
September 12, 2017<\/div>
POST<\/div><\/div>

Getting to Know the New MIPI Alliance I3C Standard<\/a><\/h3>
SIPware Webinars<\/span><\/div>
Getting to Know the New MIPI Alliance I3CSM\u00a0Standard Mobile devices today contain a rich assortment of sensors that need to communicate their\u2026<\/div><\/div><\/article>
July 1, 2017<\/div>
Simulation Standard<\/div><\/div>

Calculating Failures In Time Rates for FinFET Circuits Using TCAD<\/a><\/h3>
In a previous article in Simulation Standard article entitled \u201cSoft Error Simulations\u201d, we discussed various ways to simulate soft errors using either\u2026<\/div><\/div><\/article>
July 1, 2017<\/div>
Simulation Standard<\/div><\/div>

Optical Simulation of Liquid Crystals in the In-plane Switching Mode<\/a><\/h3>
Liquid Crystals (LCs) are widely used in the display technology due to the property of optical birefringence. Being sandwiched by two crossed\u2026<\/div><\/div><\/article>
July 1, 2017<\/div>
Simulation Standard<\/div><\/div>

TCAD Simulations of TFET and Tunneling Diode<\/a><\/h3>
Researchers and designers are looking into a future of ultra-low power and ultra-low voltage (ULV) devices and designs. Portable devices, nodes, and\u2026<\/div><\/div><\/article>
July 1, 2017<\/div>
Simulation Standard<\/div><\/div>

TFT Panel Simulation Using SmartSpice Pro<\/a><\/h3>
TFT panels have already gained their undisputable reputation in a variety of professional and commercial applications. High quality, ease of customization, and\u2026<\/div><\/div><\/article>
May 16, 2017<\/div>
POST<\/div><\/div>

Accelerating TFT and FPD Design<\/a><\/h3>
TCAD Webinars<\/span><\/div>
Accelerating TFT and FPD Design This webinar will provide an overview of different techniques for TFT and FPD design enabled by the\u2026<\/div><\/div><\/article>
May 4, 2017<\/div>
POST<\/div><\/div>

Enabling TCAD for TFT, LCD & OLED Display Designs<\/a><\/h3>
TCAD Webinars<\/span><\/div>
Enabling TCAD for TFT, LCD & OLED Display Designs This webinar will provide an insight into different TCAD-based simulation techniques that designers\u2026<\/div><\/div><\/article>
April 20, 2017<\/div>
Custom Webinars<\/div><\/div>

Get a Head Start on Reliability Analysis Early in Your Design Cycle<\/a><\/h3>
Get a Head Start on Reliability Analysis Early in Your Design Cycle Power integrity issues must be addressed as early in the\u2026<\/div><\/div><\/article>
April 1, 2017<\/div>
Simulation Standard<\/div><\/div>

Model Extraction for Body-Biased XDMOS Devices<\/a><\/h3>
Compared with regular MOSFET devices, the body bias effect in HVMOS is usually more pronounced. In addition to the regular threshold voltage\u2026<\/div><\/div><\/article>
April 1, 2017<\/div>
Simulation Standard<\/div><\/div>

Edge Effect Analysis on TFT Devices Using 3D Numerical Simulation<\/a><\/h3>
3D TFT analysis has been getting lots of attention due to issues caused by 3D effects such as the edge effect on\u2026<\/div><\/div><\/article>
April 1, 2017<\/div>
Simulation Standard<\/div><\/div>

3D Simulation of Dual-Gate Thin Film Transistors<\/a><\/h3>
Dual-Gate Thin Film Transistors (DGTFTs) are often used in pixel driver and peripheral circuits for liquid crystal displays. This is because of\u2026<\/div><\/div><\/article>
April 1, 2017<\/div>
Simulation Standard<\/div><\/div>

Effect of Fin Thickness on Subthreshold Characteristics of 10 nm FinFETs Using 3D TCAD<\/a><\/h3>
The planar bulk Si metal-oxide semiconductor field-effect transistor (MOSFET) has reached its scaling limit due to various short channel effects (SCE). With\u2026<\/div><\/div><\/article>
March 23, 2017<\/div>
Custom Webinars<\/div><\/div>

Secrets of Parasitic Extraction Unveiled<\/a><\/h3>
Secrets of Parasitic Extraction Unveiled! Parasitic extraction is a mandatory step for physical design sign off, and at advanced nodes, parasitics substantially\u2026<\/div><\/div><\/article>
February 17, 2017<\/div>
POST<\/div><\/div>

Simulating Total Dose, Prompt Dose, Damaging Fluence and SEU using TCAD<\/a><\/h3>
TCAD Webinars<\/span><\/div>
Simulating Total Dose, Prompt Dose, Damaging Fluence and SEU using TCAD This webinar will provide specific approaches for simulating electronic device behavioral\u2026<\/div><\/div><\/article>
January 26, 2017<\/div>
POST<\/div><\/div>

TCAD Simulation of Organic Optoelectronic Devices<\/a><\/h3>
TCAD Webinars<\/span><\/div>
TCAD Simulation of Organic Optoelectronic Devices This webinar will introduce Radiant developed as an integrated simulation environment of LED and OLED devices\u2026<\/div><\/div><\/article>
January 1, 2017<\/div>
Simulation Standard<\/div><\/div>

Simulation of a Bipolar Junction Transistor Under High and Low Current Injection Conditions<\/a><\/h3>
Semiconductor devices such as bipolar power transistors and solar cells may operate over a range of optical or electrical injection levels. In\u2026<\/div><\/div><\/article>
January 1, 2017<\/div>
Simulation Standard<\/div><\/div>

Thermo-mechanical Stress in Through-Silicon-Vias<\/a><\/h3>
During the last several years, the enhancement of integrated circuits (ICs) performance and power consumption have contributed to the continual scaling down\u2026<\/div><\/div><\/article>
January 1, 2017<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips and Solutions – Extract geometric information from 3D process simulation<\/a><\/h3>
Q: How do I extract geometric information, such as material thickness or junction depth, from the current 3D process simulation using Victory\u2026<\/div><\/div><\/article>
December 8, 2016<\/div>
POST<\/div><\/div>

Victory Process 2D – An Innovative Alternative to SUPREM-based Simulators Ensuring Robust 3D Solutions<\/a><\/h3>
TCAD Webinars<\/span><\/div>
Victory Process 2D – An Innovative Alternative to SUPREM-based Simulators Ensuring Robust 3D Solutions Two-dimensional process simulators based on SUPREM-IV from Stanford\u2026<\/div><\/div><\/article>
November 10, 2016<\/div>
POST<\/div><\/div>

Statistical Analysis Flow for Analog Design with VarMan<\/a><\/h3>
Variation Webinars<\/span><\/div>
Statistical Analysis Flow for Analog Design with VarMan The impact of variation on analog design has become critical with the advanced nodes\u2026<\/div><\/div><\/article>
October 1, 2016<\/div>
Simulation Standard<\/div><\/div>

TCAD Simulation of Impact Ionization at Cryogenic Temperatures, down to 3 K<\/a><\/h3>
Some electronic devices operate at very low, cryogenic temperatures, sometimes as low as 4 K, which is the temperature of liquid helium.\u2026<\/div><\/div><\/article>
October 1, 2016<\/div>
Simulation Standard<\/div><\/div>

Stress Induced by Intrinsically Strained Silicon Nitride Passivation Films of AlGaN\/GaN HEMTs Using Victory Process 2D<\/a><\/h3>
In the AlGaN\/GaN HEMT fabrication process, silicon nitride (Si3N4) passivation of the HEMT surface layer, which is typically AlGaN, is commonly used\u2026<\/div><\/div><\/article>
October 1, 2016<\/div>
Simulation Standard<\/div><\/div>

Victory Process 2D \u2013 A Valuable Alternative To SUPREM-based Simulators<\/a><\/h3>
SUPREM-IV \u2013 Stanford University PRocEss Modeling Program was first released 30 years ago. Since then its descendants - Athena from Silvaco and\u2026<\/div><\/div><\/article>
September 27, 2016<\/div>
POST<\/div><\/div>

TCAD Simulation of Organic Optoelectric Devices<\/a><\/h3>
TCAD Webinars<\/span><\/div>
This webinar will introduce Radiant developed as an integrated simulation environment of LED and OLED devices and will focus on an OLED<\/div><\/div><\/article>
September 14, 2016<\/div>
IP<\/div><\/div>

Semiconductor IP Community Joins Forces To Launch IP Tradeshow and Conference<\/a><\/h3>
Semiconductor IP Community Joins Forces To Launch IP Tradeshow and Conference REUSE 2016 Event Focuses Exclusively on Fastest Growing Segment of the\u2026<\/div><\/div><\/article>
August 9, 2016<\/div>
POST<\/div><\/div>

WeEn Semiconductors Selects Silvaco\u2019s TCAD Products for Advanced Bipolar Power Device Design<\/a><\/h3>
TCAD News<\/span><\/div>
August 9, 2016<\/div><\/div><\/article>
July 26, 2016<\/div>
Custom Webinars<\/div><\/div>

Power Distribution Network Analysis for Layout Engineers<\/a><\/h3>
Power Distribution Network Analysis for Layout Engineers This webinar will provide an overview of Silvaco\u2019s new reliability analysis tool InVar Prime. InVar\u2026<\/div><\/div><\/article>
July 1, 2016<\/div>
Simulation Standard<\/div><\/div>

Simulation of Device Degradation Due to Bias Temperature Stress<\/a><\/h3>
Introduction Bias Temperature Instability (BTI) [1] ranks among the most serious reliability issues in present-day semiconductor devices. In pMOSFETs, for instance, it\u2026<\/div><\/div><\/article>
July 1, 2016<\/div>
Simulation Standard<\/div><\/div>

Using Victory Process to Create Realistic Structures for Capacitance Extraction in Clever<\/a><\/h3>
Silvaco offers many alternatives for creating simple 3D structures, the optimum choice depending on what the user needs to simulate. Many of\u2026<\/div><\/div><\/article>
July 1, 2016<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips and Solutions – How to best visualize vectors and field lines in TonyPlot<\/a><\/h3>
Traditionally, visualizing vectors by means of arrows in TonyPlot was a challenge, especially in the areas where the computational grid was dense.\u2026<\/div><\/div><\/article>
July 1, 2016<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips and Solutions – Scattering mechanisms contributing to reduced channel mobility in 4H-SiC MOSFETs<\/a><\/h3>
In a MOSFET structure, silicon carbide, 4H-SiC in particular, is known to exhibit lower channel mobility than Si, mainly due to Coulomb\u2026<\/div><\/div><\/article>
June 30, 2016<\/div>
POST<\/div><\/div>

TCAD Usability: DeckBuild and Virtual Wafer Fab<\/a><\/h3>
TCAD Webinars<\/span><\/div>
TCAD Usability: DeckBuild and Virtual Wafer Fab This webinar will give a demonstration of the tools DeckBuild and Virtual Wafer Fab, which\u2026<\/div><\/div><\/article>
June 28, 2016<\/div>
IP<\/div><\/div>

Silvaco Expands Automotive IP Portfolio With Release of CAN FD Core<\/a><\/h3>
Silvaco Expands Automotive IP Portfolio With Release of CAN FD Core Collaboration with NXP Semiconductor Provides Customers with Key Roadmap Technology for\u2026<\/div><\/div><\/article>
June 23, 2016<\/div>
POST<\/div><\/div>

TCAD Simulation of Wide Bandgap Power Devices – English<\/a><\/h3>
TCAD Webinars<\/span><\/div>
TCAD Simulation of Wide Bandgap Power Devices Simulation of wide bandgap power devices has always posed convergence challenges. In addition to this,\u2026<\/div><\/div><\/article>
May 24, 2016<\/div>
POST<\/div><\/div>

TCAD Simulation of Wide Bandgap Power Devices – Japanese<\/a><\/h3>
TCAD Webinars<\/span><\/div>
TCAD Simulation of Wide Bandgap Power Devices Simulation of wide bandgap power devices has always posed convergence challenges. In addition to this\u2026<\/div><\/div><\/article>
April 28, 2016<\/div>
POST<\/div><\/div>

Simulation of Physical Etching in Memory Technology<\/a><\/h3>
TCAD Webinars<\/span><\/div>
Simulation of Physical Etching in Memory Technology This webinar will provide a deep insight into the methods, mechanisms and models to simulate\u2026<\/div><\/div><\/article>
April 14, 2016<\/div>
POST<\/div><\/div>

Efficient 3D TCAD Simulation of Silicon Power Devices<\/a><\/h3>
TCAD Webinars<\/span><\/div>
Efficient 3D TCAD Simulation of Silicon Power Devices It is well known that TCAD simulation can save time and money since it\u2026<\/div><\/div><\/article>
April 1, 2016<\/div>
Simulation Standard<\/div><\/div>

Soft Error<\/a><\/h3>
A soft error in the context of this article, can be defined as an unintended change in electrical state of a device\u2026<\/div><\/div><\/article>
April 1, 2016<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips and Solutions – Types of 3D Delaunay Shape Refinement<\/a><\/h3>
Q: What Types of 3D Delaunay Shape Refinement can be used in Victory Process? A. The Victory Process cell mode Delaunay 3D\u2026<\/div><\/div><\/article>
March 31, 2016<\/div>
POST<\/div><\/div>

Variation aware design for advanced nodes and low power technologies<\/a><\/h3>
Variation Webinars<\/span><\/div>
Variation aware design for advanced nodes and low power technologies Designers’ characterization and verification tasks have become more critical due to scaled\u2026<\/div><\/div><\/article>
March 17, 2016<\/div>
Custom Webinars<\/div><\/div>

Easy design migration to Silvaco Custom Design flow via OpenAccess<\/a><\/h3>
Easy design migration to Silvaco Custom Design flow via OpenAccess This webinar will provide an overview for how circuit designers can use\u2026<\/div><\/div><\/article>
March 17, 2016<\/div>
Custom Webinars<\/div><\/div>

Easy design migration to Silvaco Custom Design flow via OpenAccess<\/a><\/h3>
Easy design migration to Silvaco Custom Design flow via OpenAccess This webinar will provide an overview for how circuit designers can use\u2026<\/div><\/div><\/article>
January 1, 2016<\/div>
Simulation Standard<\/div><\/div>

Blue LED Simulation<\/a><\/h3>
It is very important to understand the operation and underlying physics of InGaN\/GaN materials based electronic device in modern display industry such\u2026<\/div><\/div><\/article>
January 1, 2016<\/div>
Simulation Standard<\/div><\/div>

Unified Victory Conformal Export for 2D Process Mode<\/a><\/h3>
Victory Process can operate in either 1, 2 or 3-dimensions and can produce one of two different geometric representations: cell mode and\u2026<\/div><\/div><\/article>
January 1, 2016<\/div>
Simulation Standard<\/div><\/div>

a-IGZO TFT Simulation<\/a><\/h3>
The flat panel device for active matrix liquid crystal displays (AMLCDs) and active matrix organic light-emitting diode displays (AMOLEDs) has utilized a\u2026<\/div><\/div><\/article>
January 1, 2016<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips and Solutions – Crop and Slice using a non-convex mask in Victory Process export<\/a><\/h3>
Q. How can I Crop and Slice using a non-convex mask during the export? Non-Convex Mask Polygons Non-Convex Mask Polygons Previous Victory\u2026<\/div><\/div><\/article>
December 16, 2015<\/div>
POST<\/div><\/div>

Solar cell modeling using TCAD and SPICE<\/a><\/h3>
Modeling Webinars<\/span>SPICE Webinars<\/span>TCAD Webinars<\/span><\/div>
Solar Cell Modeling Using TCAD and SPICE In this webinar a review of the TCAD-to-SPICE simulation flow of solar cells and solar\u2026<\/div><\/div><\/article>
October 1, 2015<\/div>
Simulation Standard<\/div><\/div>

Performance Evaluation of a New Hybrid MPI-thread Parallelized Direct Solver<\/a><\/h3>
The solution of linear systems lies in the core of any TCAD simulation. On any nonlinear step of the computation a linear\u2026<\/div><\/div><\/article>
October 1, 2015<\/div>
Simulation Standard<\/div><\/div>

Deep Hole Etching Simulation for Advanced NAND Flash Memory<\/a><\/h3>
The NAND Flash memory cell has been refined to reduce the bit cost, but the limit of its miniaturization has been reached\u2026<\/div><\/div><\/article>
October 1, 2015<\/div>
Simulation Standard<\/div><\/div>

Optical Simulation of Organic Light Emitting Diode by Transfer Matrix Method with a Green\u2019s Function Approach and 2D FDTD<\/a><\/h3>
Organic light emitting diode (OLED) has been getting much attention over the past decades in the field of displays and lighting applications\u2026<\/div><\/div><\/article>
October 1, 2015<\/div>
Simulation Standard<\/div><\/div>

3D TCAD Mixed-Mode Simulation of Current Filaments in IGBT Multicell Array under Short-Circuit Condition<\/a><\/h3>
A power IGBT (Insulated Gate Bipolar Transistor) is conventionally made up of a repetitive array of homogenous IGBT cells. Such a homogenous\u2026<\/div><\/div><\/article>
October 1, 2015<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips and Solutions – Create scalable devices with Victory Process<\/a><\/h3>
Deckbuild supports variable substitution for both numerical and string variables using the SET statement and the $ symbol, thus allowing users to\u2026<\/div><\/div><\/article>
September 29, 2015<\/div>
Custom Webinars<\/div><\/div>

Power Integrity and Reliability Analysis<\/a><\/h3>
Power Integrity and Reliability Analysis This webinar will provide an overview of Silvaco\u2019s power integrity and reliability analysis tool, InVar. InVar\u2019s concurrent\u2026<\/div><\/div><\/article>
September 29, 2015<\/div>
Custom Webinars<\/div><\/div>

Power Integrity and Reliability Analysis<\/a><\/h3>
Power Integrity and Reliability Analysis This webinar will provide an overview of Silvaco\u2019s power integrity and reliability analysis tool, InVar. InVar\u2019s concurrent\u2026<\/div><\/div><\/article>
July 1, 2015<\/div>
Simulation Standard<\/div><\/div>

Improvements and Features of the Updated DeckBuild 2 GUI<\/a><\/h3>
In this article we will emphasize the new features and improvements of the DeckBuild 2 deck editing environment. We will start by\u2026<\/div><\/div><\/article>
July 1, 2015<\/div>
Simulation Standard<\/div><\/div>

Performance Improvement by MPI Parallelization in 3D Device Simulation<\/a><\/h3>
As the design technology for power devices, such as MOSFET, GTO, and IGBT has matured, the importance of large domain 3D TCAD\u2026<\/div><\/div><\/article>
July 1, 2015<\/div>
Simulation Standard<\/div><\/div>

Electrical Simulation of Liquid Crystals<\/a><\/h3>
Liquid Crystals (LCs) are state of matter intermediate between that of a crystalline and a liquid. The optical, mechanical, electrical and magnetic\u2026<\/div><\/div><\/article>
July 1, 2015<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips and Solutions – Local conformal mesh refinement in Victory Process<\/a><\/h3>
The Victory Process conformal export is generated from the volume planes specified in a user deck. The accuracy and resolution of the\u2026<\/div><\/div><\/article>
May 1, 2015<\/div>
Custom Webinars<\/div><\/div>

Partitioning and DRC for 3D systems & ICs<\/a><\/h3>
Partitioning and DRC for 3D systems & ICs 3D integration of ICs and systems is enhancing cost scaling of \u201cMore than Moore\u201d\u2026<\/div><\/div><\/article>
May 1, 2015<\/div>
Custom Webinars<\/div><\/div>

Partitioning and DRC for 3D systems & ICs<\/a><\/h3>
Partitioning and DRC for 3D systems & ICs 3D integration of ICs and systems is enhancing cost scaling of \u201cMore than Moore\u201d\u2026<\/div><\/div><\/article>
April 1, 2015<\/div>
Simulation Standard<\/div><\/div>

Radiant: GUI-based Design Software for Performing Simulations of Optoelectronic Thin Film Devices Such as LED and OLED<\/a><\/h3>
Device simulation helps users understand and depict the physical processes in a device and to make reliable predictions of the behavior of\u2026<\/div><\/div><\/article>
April 1, 2015<\/div>
Simulation Standard<\/div><\/div>

Optimizing Solar Cell Top Metal Contact Design Introduction<\/a><\/h3>
Among the many design criteria for solar cells, the design of the top metal contact impacts the cell efficiency. The areal density\u2026<\/div><\/div><\/article>
April 1, 2015<\/div>
Simulation Standard<\/div><\/div>

Vertical LOCOS Power Devices in Victory Process: From 3D Process and Electrical Optimisation to High Speed, Full Chip Process Emulation<\/a><\/h3>
There is a constant demand to lower the on-state resistance of devices, improving their energy efficiency as well as increasing their current\u2026<\/div><\/div><\/article>
April 1, 2015<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips and Solutions – Mirror 3D structures in Victory Process<\/a><\/h3>
Victory Process supports mesh generation for device simulation using many common algorithms. The primary two are conformal and delaunay. A simple process\u2026<\/div><\/div><\/article>
March 28, 2015<\/div>
POST<\/div><\/div>

High Voltage Power Device Modeling with HiSIM_HV 2<\/a><\/h3>
Modeling Webinars<\/span><\/div>
High Voltage Power Device Modeling with HiSIM_HV 2 This webinar will provide a comprehensive overview of model parameter extraction for high voltage\u2026<\/div><\/div><\/article>
February 17, 2015<\/div>
POST<\/div><\/div>

Simulating Total Dose, Prompt Dose, Damaging Fluence and SEU using TCAD<\/a><\/h3>
TCAD Webinars<\/span><\/div>
Simulating Total Dose, Prompt Dose, Damaging Fluence and SEU using TCAD This webinar will provide specific approaches for simulating electronic device behavioral\u2026<\/div><\/div><\/article>
January 1, 2015<\/div>
Simulation Standard<\/div><\/div>

Plasmonic Light Trapping Transforming Thin-Film Photovoltaics<\/a><\/h3>
The photovoltaics (PV) market represents the fastest growing renewable energy technology, with a 35% annual growth rate, which is projected to be\u2026<\/div><\/div><\/article>
January 1, 2015<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips, and Solutions – Defining VWF Curve Target For Curve Calibration<\/a><\/h3>
VWF allows a curve as target for optimization. This feature greatly benefits the users who need to calibrate TCAD simulation against measured\u2026<\/div><\/div><\/article>
January 1, 2015<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips, and Solutions – Crop and Slice in the Victory Process 3D Exports<\/a><\/h3>
This document is a short guide on the new and existing support for export cropping\/slicing in Victory Process cell mode. The cropping\u2026<\/div><\/div><\/article>
January 1, 2015<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips and Solutions – Develop your own etch model in Victory Process<\/a><\/h3>
Background: Victory Process is packaged with a wide range of etch models. Victory Process also supports an \u201cOpen Modelling Interface\u201d (OMI). The\u2026<\/div><\/div><\/article>
October 1, 2014<\/div>
Simulation Standard<\/div><\/div>

Simulating Radiation-Induced Shifts in MOSFET Threshold Voltage<\/a><\/h3>
Irradiation by energetic particles can degrade semiconductor device performance. The particles involved can be electrons, positrons, neutrons, protons, alpha particles, heavy ions,\u2026<\/div><\/div><\/article>
October 1, 2014<\/div>
Simulation Standard<\/div><\/div>

Mixed Mode Radiation Event Detector<\/a><\/h3>
A reversed biased PIN diode acts as a radiation event detector, sensing the occurrence of an ionizing radiation pulse, which is connected\u2026<\/div><\/div><\/article>
October 1, 2014<\/div>
Simulation Standard<\/div><\/div>

Displacement Damage<\/a><\/h3>
Two fundamental damage mechanisms take place when devices are exposed to particle fluences: ionization and lattice displacement or just displacement damage. Ionization\u2026<\/div><\/div><\/article>
October 1, 2014<\/div>
Simulation Standard<\/div><\/div>

Radiation-Induced Current Leakage Between Two n-MOSFET\u2019s<\/a><\/h3>
The Simulation Standard article \u201cSimulating Radiation-Induced Shifts in MOSFET Threshold Voltage\u201d1 gives a brief overview of the ways that ionizing radiation can\u2026<\/div><\/div><\/article>
July 1, 2014<\/div>
Simulation Standard<\/div><\/div>

Multiple SEU Strike Simulations on a Six Transistor 20nm SRAM Cell<\/a><\/h3>
It is often not realized that more than one Single Event Upset (SEU) statement can be used in a simulation. Each SEU\u2026<\/div><\/div><\/article>
July 1, 2014<\/div>
Simulation Standard<\/div><\/div>

The Physics of Single Event Burnout (SEB)<\/a><\/h3>
Single Event Burnout in a diode, requires a specific set of circumstances to occur, since there is no intrinsic current gain in\u2026<\/div><\/div><\/article>
July 1, 2014<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips, and Solutions – Types of 3D Delaunay Shape Refinement in Victory Process<\/a><\/h3>
The Victory Process cell mode Delaunay 3D device meshing algorithm already includes various TCAD-based local refinement algorithms to ensure accurate and robust\u2026<\/div><\/div><\/article>
July 1, 2014<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips and Solutions – Meshing a Non Axis Aligned SEU Beam<\/a><\/h3>
Q: I have an SEU beam in a 2D structure; the beam track is at an angle through the device. I don\u2019t\u2026<\/div><\/div><\/article>
April 1, 2014<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips, and Solutions – Calculate Light Extraction Efficiency in an OLED or LED with Pure Optical Simulation<\/a><\/h3>
Calculation of light extraction efficiency or optical output coupling efficiency is often needed in simulating a light emitting device (LED) such as\u2026<\/div><\/div><\/article>
April 1, 2014<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips, and Solutions – Achieve Publication Quality Plots Using TonyPlot<\/a><\/h3>
Yes, TonyPlot has many various display and preference settings that users can adjust, transforming their simulation data into a high quality plot\u2026<\/div><\/div><\/article>
April 1, 2014<\/div>
Simulation Standard<\/div><\/div>

Simulations of Deep-Level Transient Spectroscopy for 4H-SiC<\/a><\/h3>
Silicon carbide is expected to be an excellent device material as high voltage and low-loss power devices. Recently, SBD (Schottky Barrier Diode)\u2026<\/div><\/div><\/article>
April 1, 2014<\/div>
Simulation Standard<\/div><\/div>

Generally Applicable Degradation Model for Silicon MOS Devices<\/a><\/h3>
The main cause of operational degradation in MOS devices is believed to be due to the buildup of charge at the Silicon-Oxide\u2026<\/div><\/div><\/article>
March 27, 2014<\/div>
POST<\/div><\/div>

Leakage Current TCAD Calibration in a-Si TFTs<\/a><\/h3>
TCAD Webinars<\/span><\/div>
Leakage Current TCAD Calibration in a-Si TFTs This webinar will outline in detail a calibration procedure used for amorphous silicon Thin-Film Transistors\u2026<\/div><\/div><\/article>
February 27, 2014<\/div>
POST<\/div><\/div>

TCAD to SPICE simulation of SiC and Si Power Devices<\/a><\/h3>
SPICE Webinars<\/span>TCAD Webinars<\/span><\/div>
TCAD to SPICE Simulation of SiC and Si Power Devices – Archive This webinar will provide a discussion of the methods used\u2026<\/div><\/div><\/article>
January 27, 2014<\/div>
POST<\/div><\/div>

Modeling and Analysis of Single Event Effects<\/a><\/h3>
TCAD Webinars<\/span><\/div>
Modeling and Analysis of Single Event Effects – Archives This webinar will provide a discussion of the methods used by radiation effects\u2026<\/div><\/div><\/article>
January 1, 2014<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips, and Solutions – Simulation on a Cluster of Computers Using the Distributed Computing Feature<\/a><\/h3>
A new feature that is introduced in Silvaco\u2019s TCAD applications allows the user to run a parallel simulation on a cluster of\u2026<\/div><\/div><\/article>
January 1, 2014<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips and Solutions – Illuminate a 3D device in a Victory Device Opto-electronic Simulation<\/a><\/h3>
A: The 2 basic commands needed to illuminate a structure in Victory Device are\u00a0BEAM\u00a0and\u00a0SOLVE. A single (or multiple)\u00a0BEAM\u00a0statement(s) are specified containing the\u2026<\/div><\/div><\/article>
January 1, 2014<\/div>
Simulation Standard<\/div><\/div>

Atlas Simulation of GaN-Based Super Heterojunction Field Effect Transistors Using the Polarization Junction Concept<\/a><\/h3>
Wide-bandgap semiconductors such as SiC and GaN have attracted much attention because they are expected to break through the material limits of\u2026<\/div><\/div><\/article>
January 1, 2014<\/div>
Simulation Standard<\/div><\/div>

Modeling the Optical Response of Phonon-dressed Excitons in OLED Simulations<\/a><\/h3>
We demonstrate the modeling of optical response of exciton-polarons based on the well established Holstein Hamiltonian to model coupled exciton-phonon systems in\u2026<\/div><\/div><\/article>
October 1, 2013<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips, and Solutions – Simulate Rapid Thermal Annealing Temperature Transients in Vacuum<\/a><\/h3>
When a wafer is clamped only at its edges and is heated with an infra-red source in a vacuum, the majority of\u2026<\/div><\/div><\/article>
October 1, 2013<\/div>
Simulation Standard<\/div><\/div>

Atlas Simulation of a Wide Bandgap Gallium Oxide (Ga2O3) MOSFET<\/a><\/h3>
Single-crystal gallium oxide (Ga2O3) has attracted increasing attention as a promising material for power device applications. It possesses excellent material properties and\u2026<\/div><\/div><\/article>
October 1, 2013<\/div>
Simulation Standard<\/div><\/div>

Simulation of a DBR Edge Emitting Laser with External Air Gap Tuning Mirror<\/a><\/h3>
A methodology for simulating an edge emitting laser is demonstrated that incorporates a distributed Bragg Re\ufb02ector (DBR) as one of the mirrors,\u2026<\/div><\/div><\/article>
July 1, 2013<\/div>
Simulation Standard<\/div><\/div>

Anode Shorts Layout Dependence of Bi-mode IGBT (BiGT) On-state Characteristics<\/a><\/h3>
A new class of high-voltage semiconductor devices, known as a reverse conducting IGBT (RC-IGBT), has emerged in recent years from research efforts\u2026<\/div><\/div><\/article>
July 1, 2013<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips and Solutions – Compare the Results of Breakdown Simulations with Hatakeyama\u2019s Impact Ionization Model for 4H-SiC Based Power Devices<\/a><\/h3>
In a 4H-SiC crystal, the stacking sequence of a Si-C bilayer plane extends along the crystallographic c-axis direction, also referred to as\u2026<\/div><\/div><\/article>
July 1, 2013<\/div>
Simulation Standard<\/div><\/div>

2D IBC-SHJ Solar Cell Simulation and Optimization<\/a><\/h3>
Interdigitated back contact silicon heterojunction (IBC-SHJ) combines the advantages of interdigitated back contact (IBC) and silicon heterojunction (SHJ) solar cells. Having all\u2026<\/div><\/div><\/article>
July 1, 2013<\/div>
Simulation Standard<\/div><\/div>

State of the Art 2D and 3D Process and Device Simulation of GaN-Based Devices<\/a><\/h3>
Silicon has long been the semiconductor of choice for high-voltage power electronics applications. However, wide-bandgap semiconductors such as SiC and GaN have\u2026<\/div><\/div><\/article>
April 1, 2013<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips and Solutions – Setup Athena Monte Carlo Simulation of Ion Implantation in Silicon Carbide<\/a><\/h3>
Monte Carlo module of Athena allows accurate simulation of ion implantation in 4H-SiC and 6H-SiC [1]. It is known that channeling effects\u2026<\/div><\/div><\/article>
April 1, 2013<\/div>
Simulation Standard<\/div><\/div>

TCAD Simulation of Multiple Quantum Well Infrared Photodetector (QWIP)<\/a><\/h3>
We demonstrate the capabilities of SILVACO TCAD tools for the design and simulation of intersubband GaAs\/AlGaAs multiple quantum well infrared photodetectors. We\u2026<\/div><\/div><\/article>
April 1, 2013<\/div>
Simulation Standard<\/div><\/div>

The Extended Gaussian Disorder Model in Atlas<\/a><\/h3>
In this article the various enhancements to the organic device modeling that have been implemented recently in Atlas are presented. Following the\u2026<\/div><\/div><\/article>
April 1, 2013<\/div>
Simulation Standard<\/div><\/div>

Simulation of Ion Beam Etching of Patterned Nanometer-scale Magnetic Structures for High-Density Storage Applications<\/a><\/h3>
Fabrication of various nano-structures often requires mask controlled or patterned etching of materials. The chemical or wet etch methods cannot be used\u2026<\/div><\/div><\/article>
January 1, 2013<\/div>
Simulation Standard<\/div><\/div>

State of the Art 3D SiC Process and Device Simulation<\/a><\/h3>
Silicon has long been the semiconductor of choice for high-voltage power electronics applications [1,2]. However, wide-bandgap semiconductors such as SiC have begun\u2026<\/div><\/div><\/article>
October 1, 2012<\/div>
Simulation Standard<\/div><\/div>

Calibration of the Ion Enhanced Chemical Etching Model of VICTORY Process Using Virtual Wafer Fab<\/a><\/h3>
In this article we describe a technique to automatically calibrate parameters of an Ion Enhanced Chemical Etching model implemented in the 3D\u2026<\/div><\/div><\/article>
October 1, 2012<\/div>
Simulation Standard<\/div><\/div>

Using VICTORY Process to Model the Effect of Silicon Substrate Orientation on Oxidation Kinetics<\/a><\/h3>
Different crystal planes of silicon are known to have different oxidation rates, e.g. the silicon plane with Miller indices is oxidized approximately\u2026<\/div><\/div><\/article>
October 1, 2012<\/div>
Simulation Standard<\/div><\/div>

A Semi-Empirical Model for the Simulation of Ion Milling in VICTORY Process<\/a><\/h3>
The three-dimensional process simulator VICTORY Process now includes a semi-empirical model for the simulation of ion milling. During ion milling, the mill\u2026<\/div><\/div><\/article>
October 1, 2012<\/div>
Simulation Standard<\/div><\/div>

Developing Custom Etching\/Deposition Models in VICTORY Process<\/a><\/h3>
VICTORY Process is supplied with a wide range of models and data for an extensive set of materials, so that you can\u2026<\/div><\/div><\/article>
July 1, 2012<\/div>
Simulation Standard<\/div><\/div>

Simulation of Stress Evolution During Semiconductor Device Fabrication<\/a><\/h3>
Accurate stress simulation has become a necessary part of performance and reliability analysis of semiconductor devices. In our previous paper [1] we\u2026<\/div><\/div><\/article>
July 1, 2012<\/div>
Simulation Standard<\/div><\/div>

Actuation Voltage For a Cantilever Switch in MEMS<\/a><\/h3>
Following the successful 3D simulation of the process flow of cantilever based MEMS switches using VICTORY Process is presented in August 2005\u2026<\/div><\/div><\/article>
April 1, 2012<\/div>
Simulation Standard<\/div><\/div>

Current Collapse Phenomenon in GaN HFETs resulting from Intentional Bulk Iron (Fe) Doping and Un-intentional Interface Traps<\/a><\/h3>
The Gallium Nitride-based material family has fundamental material properties which make it an attractive candidate for semiconductor device fabrication. These properties include:\u2026<\/div><\/div><\/article>
April 1, 2012<\/div>
Simulation Standard<\/div><\/div>

Syntax Driven 2D Structure Export from 3D Structures and Extraction of 2D Volume Data Maps<\/a><\/h3>
This article demonstrates a new feature of TonyPlot3D. This feature enables the automated, syntax driven export of 2D structure slices from 3D\u2026<\/div><\/div><\/article>
April 1, 2012<\/div>
Simulation Standard<\/div><\/div>

Leakage Current Calibration Procedures of Amorphous Silicon Thin-Film Transistors<\/a><\/h3>
Amorphous silicon Thin-Film Transistors (a-Si TFTs) are widely used as the switching device of liquid crystal display (LCD) technology. For development and\u2026<\/div><\/div><\/article>
April 1, 2012<\/div>
Simulation Standard<\/div><\/div>

3D TFT Simulation<\/a><\/h3>
Both flexible and touch panel displays have become popular for portable applications. To meet various functional requirements, system-on-panel (SOP) design has become\u2026<\/div><\/div><\/article>
January 1, 2012<\/div>
Simulation Standard<\/div><\/div>

The Studies of Anti-Reflective (AR) Coatings Effects for Solar Cell by Using Silvaco TCAD Tools<\/a><\/h3>
In 1975, screen printing was first applied to solar cells for the formation of the front and rear contacts replacing expensive vacuum\u2026<\/div><\/div><\/article>
January 1, 2012<\/div>
Simulation Standard<\/div><\/div>

Geiger Mode Simulation of Avalanche Photodiodes in ATLAS<\/a><\/h3>
Single-photon counting detectors are used in a wide range of applications, including astronomy, optical communications, biological sensors, and military uses. Photomultiplier tubes\u2026<\/div><\/div><\/article>
January 1, 2012<\/div>
Simulation Standard<\/div><\/div>

ZnO based LED: A Performance Optimization through TCAD Simulation<\/a><\/h3>
In this paper, a two dimensional (2-D) generic model of quantum well light emitting diode (LED) based on ZnO, II-VI compound semiconductors\u2026<\/div><\/div><\/article>
January 1, 2012<\/div>
Simulation Standard<\/div><\/div>

Normally-off AlGaN\/GaN HFET with p-type GaN Gate and AlGaN Buffer<\/a><\/h3>
To break through the material limits of Silicon and to realize the drastic performance improvement needed to meet the severe requirements in\u2026<\/div><\/div><\/article>
January 1, 2012<\/div>
Simulation Standard<\/div><\/div>

Simulation of Stresses and Mobility Enhancement Factors in 3D Inverter Cell<\/a><\/h3>
The analysis and characterization of stress effects have become an integral part of semiconductor technology and device design. In a typical semiconductor\u2026<\/div><\/div><\/article>
September 1, 2011<\/div>
Simulation Standard<\/div><\/div>

High Light Extraction on OLED with Microcavity Effects<\/a><\/h3>
OLEDs have been researched for application in display devices due to their considerable advantages. In order to further improve and optimize devices\u2026<\/div><\/div><\/article>
September 1, 2011<\/div>
Simulation Standard<\/div><\/div>

Modelling of GaN\/InGaN Tricolour Multiple Quantum Well Light Emitting Diodes<\/a><\/h3>
Since lighting is estimated to account for 20% of the world\u2019s electricity consumption, the search for reliable and efficient lighting technologies to\u2026<\/div><\/div><\/article>
September 1, 2011<\/div>
Simulation Standard<\/div><\/div>

InGaN\/GaN Ridge Type with MQW Laser Diode Simulation Using ATLAS<\/a><\/h3>
The light source on short wavelenghts has been researched in GaN-based lser diodes (LDs). For high efficiency emitting devices, the wave-guide layer\u2026<\/div><\/div><\/article>
September 1, 2011<\/div>
Simulation Standard<\/div><\/div>

Using VICTORY Process to Model Thermal Oxidation of Silicon in O2\/HCl Mixtures<\/a><\/h3>
The addition of a chlorine species during thermal oxidation of silicon results in improved threshold stability, higher and more uniform oxide dielectric\u2026<\/div><\/div><\/article>
July 1, 2011<\/div>
Simulation Standard<\/div><\/div>

Thermal Optimization on GaN HFET Using Flip Chip and Through Wafer via Structures<\/a><\/h3>
GaN heterojunction field effect transistors (HFETs) have been under extensive investigation because of their projected superb performances as high-power RF devices. The\u2026<\/div><\/div><\/article>
July 1, 2011<\/div>
Simulation Standard<\/div><\/div>

3D Simulation of Ion Enhanced Chemical Etching with VICTORY Process<\/a><\/h3>
VICTORY Process is a tool for 3D simulation of the semiconductor industry\u2019s technological processes. It allows stable and accurate modeling of the\u2026<\/div><\/div><\/article>
July 1, 2011<\/div>
Simulation Standard<\/div><\/div>

Simulation of Transient Diffusion Enhancement of Boron with VICTORY Process in 3D, with the Plus-One Implantation Damage Model and the Five-Stream Diffusion Model<\/a><\/h3>
VICTORY Process is a 3D process simulation tool which allows for an accurate simulation of the doping distributions in semiconductor devices. It\u2026<\/div><\/div><\/article>
April 1, 2011<\/div>
Simulation Standard<\/div><\/div>

The Studies of Regular Texture Thickness and Finger Pattern of the Front Surface by Using Silvaco TCAD Tools<\/a><\/h3>
The photovoltaic industry has rapidly grown since 2000 and has diversified in technology how the solar cell are manufactured. As of 2010,\u2026<\/div><\/div><\/article>
April 1, 2011<\/div>
Simulation Standard<\/div><\/div>

Extracting Concentrations from Arbitrary Shaped Well Regions<\/a><\/h3>
It is often the case when simulating charged coupled devices (CCDs) or image sensors, that a designer wishes to know how many\u2026<\/div><\/div><\/article>
April 1, 2011<\/div>
Simulation Standard<\/div><\/div>

Simulation of 3D Anisotropic Crystal Etching with VICTORY Process<\/a><\/h3>
Anisotropic crystal etching is the common technique used in Micro Electromechanical systems (MEMS) manufacturing. It uses the property of some single crystal\u2026<\/div><\/div><\/article>
February 1, 2011<\/div>
Simulation Standard<\/div><\/div>

Using VICTORY Process to Simulate Thermal Oxidation of Silicon at High Pressures of Ambient Gases<\/a><\/h3>
Developing ULSI silicon technology requires good control of dopant diffusion and minimizing defect formation during thermal oxidation. The use of high pressures\u2026<\/div><\/div><\/article>
January 1, 2011<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips, and Solutions – Export 3D Structures from VICTORY Cell\/Process to ANSOFT ANSYS<\/a><\/h3>
SILVACO provides the tool ANSYSExporter which establishes the link between SILVACO software and ANSOFT ANSYS. ANSYSExporter is fully integrated within the SILVACO\u2026<\/div><\/div><\/article>
January 1, 2011<\/div>
Simulation Standard<\/div><\/div>

The Doping Effect Simulation on the OLED Devices Using ATLAS<\/a><\/h3>
Organic light emitting diodes (OLEDs) have attracted great attention for full-color flat-panel displays since the demonstration of efficient electroluminescent devices [1]. Due\u2026<\/div><\/div><\/article>
January 1, 2011<\/div>
Simulation Standard<\/div><\/div>

Design Consideration & Performance Analysis of MCT Based Dual Band (MWIR\/LWIR) Photodetector<\/a><\/h3>
In this paper, a physics based two dimensional (2-D) generic model of dual band mid wavelength and long wavelength infrared (MW-LW) photodetector\u2026<\/div><\/div><\/article>
October 1, 2010<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips, and Solutions – Conversion to Different Units<\/a><\/h3>
Q. How do I convert a value from one set of units into another? A. Use the DBINTERNAL CONVERT.UNITS command.<\/div><\/div><\/article>
October 1, 2010<\/div>
Simulation Standard<\/div><\/div>

How to Mesh in 2D TCAD<\/a><\/h3>
Meshing for process in ATHENA or electrical characterisation in ATLAS is one of the biggest challenges that a user faces. Poor meshing\u2026<\/div><\/div><\/article>
October 1, 2010<\/div>
Simulation Standard<\/div><\/div>

Using VICTORY Process for Plasma Etching Simulations<\/a><\/h3>
VICTORY Process, the 3D process simulator now includes a module for plasma etching. The module is designed to simulate plasma etching processes\u2026<\/div><\/div><\/article>
July 1, 2010<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips, and Solutions – Passing a Variable from an ATLAS deck into a C-Interpreter Function<\/a><\/h3>
The Silvaco C-Interpreter (SCI) allows convenient and flexible definition of physical models and material parameters via an ANSI standard C-language interface. The\u2026<\/div><\/div><\/article>
July 1, 2010<\/div>
Simulation Standard<\/div><\/div>

Simulating Negative Bias Temperature Instability of p-MOSFETS<\/a><\/h3>
The degradation of MOSFET devices having relatively thin oxide layers is generally accepted as being mainly associated with the depassivation of silicon\u2026<\/div><\/div><\/article>
July 1, 2010<\/div>
Simulation Standard<\/div><\/div>

Coupled Optimization of Diode and IGBT Characteristics Under Clamped Inductive Switching in ATLAS MixedMode and Virtual Wafer Fab (VWF)<\/a><\/h3>
Virtual Wafer Fab\u2019s powerful range of optimizers are used to investigate and minimise the coupled switching losses of a TCAD IGBT and\u2026<\/div><\/div><\/article>
July 1, 2010<\/div>
Simulation Standard<\/div><\/div>

Using Manual Refinement of Geometrical Mesh in VICTORY Process<\/a><\/h3>
VICTORY Process is a 3D process simulation tool which employs the LevelSet technique for manipulating and deforming structures. The structure\u2019s geometry is\u2026<\/div><\/div><\/article>
April 1, 2010<\/div>
Simulation Standard<\/div><\/div>

Simulating the Hysteresis effects of Si\/SiO2 Interface Traps<\/a><\/h3>
The trap states at the interface of Silicon with Silicon Dioxide are usually divided conceptually into interface states and fixed oxide charges\u2026<\/div><\/div><\/article>
April 1, 2010<\/div>
Simulation Standard<\/div><\/div>

Designing a High-Voltage IGBT Structure with TCAD<\/a><\/h3>
The Insulated Gate Bipolar Transistor (IGBT), is a power device that combines the high-power characteristics of bipolar transistors with the fast-switching and\u2026<\/div><\/div><\/article>
April 1, 2010<\/div>
Simulation Standard<\/div><\/div>

Investigation of the SiGe Waveguide Photodiodes Using FDTD Method for High Speed Optical Communication<\/a><\/h3>
Silicon as a photonic medium has unique advantages in telecommunication systems. It is transparent in the range of optical telecommunications wavelength (1.3\u2026<\/div><\/div><\/article>
January 1, 2010<\/div>
Simulation Standard<\/div><\/div>

A Box Method Discretisation for the Drift-Diffusion Equations in a Magnetic Field<\/a><\/h3>
The problem of discretising the semiconductor drift-diffusion equations in the presence of a uniform magnetic field using the Box Method has previously\u2026<\/div><\/div><\/article>
January 1, 2010<\/div>
Simulation Standard<\/div><\/div>

Simulation of Resonant Tunneling Diodes Using ATLAS<\/a><\/h3>
This article describes a model for Resonant Tunneling Diodes (RTDs) implemented within ATLAS framework. The model is based on a self-consistent solution\u2026<\/div><\/div><\/article>
January 1, 2010<\/div>
Simulation Standard<\/div><\/div>

Modeling and Optimization of CIGS Solar Cell Module<\/a><\/h3>
Solar cells manufactured from wafers of crystalline or polycrystalline silicon are today the dominant technology in the commercial market. Solar cells based\u2026<\/div><\/div><\/article>
January 1, 2010<\/div>
Simulation Standard<\/div><\/div>

Using VICTORY PROCESS for Rapid Geometry Prototyping<\/a><\/h3>
The fully three-dimensional process simulator VICTORY PROCESS allows user to perform a wide range of manipulations of the structure\u2019s geometry in order\u2026<\/div><\/div><\/article>
October 1, 2009<\/div>
Simulation Standard<\/div><\/div>

3D SOI NMOSFET Simulation Using VICTORY DEVICE<\/a><\/h3>
SOI MOSFETs can exhibit a kink in their Id\/Vd curves, which is caused by impact ionization, floating potentials, and other effects. One\u2026<\/div><\/div><\/article>
October 1, 2009<\/div>
Simulation Standard<\/div><\/div>

Crosstalk Simulation in InSb Detector Arrays<\/a><\/h3>
Crosstalk is one of the main parameters that critically affect the resolution of detector arrays. It results in a reduction in image\u2026<\/div><\/div><\/article>
October 1, 2009<\/div>
Simulation Standard<\/div><\/div>

Simulating the Effects of Stress\/Strain on a 50 nm Silicon FinFET<\/a><\/h3>
In modern semiconductor devices, the effects of physical lattice strain are playing an increasingly important role. One reason for this is that\u2026<\/div><\/div><\/article>
July 1, 2009<\/div>
Simulation Standard<\/div><\/div>

Textured Thin-film Solar Cell Simulation<\/a><\/h3>
Texturing is often used to improve light trapping in thin film solar cells. The textured surfaces act to scatter the light in\u2026<\/div><\/div><\/article>
July 1, 2009<\/div>
Simulation Standard<\/div><\/div>

Evaluating of the Breakdown Voltage of the Super-Junctions Using ATLAS<\/a><\/h3>
High Voltage Power Devices using super junction or multi RESURF effect have a relatively high BV with a drastic reduction in the\u2026<\/div><\/div><\/article>
July 1, 2009<\/div>
Simulation Standard<\/div><\/div>

Active and Isolation Trench Fabrication for 100V Vertical LOCOS Power MOSFETS with VICTORY PROCESS and ATHENA<\/a><\/h3>
Vertical LOCOS (VLOCOS) power MOSFET structures are becoming increasingly popular [1-3] for 100 V rated applications due to their high packing density,\u2026<\/div><\/div><\/article>
July 1, 2009<\/div>
Simulation Standard<\/div><\/div>

Third Generation Solar Cell Technologies: Localized Surface Plasmons<\/a><\/h3>
Solar cells are experiencing a surge in activity due to concerns about sustainability of non-renewable resources and the negative impacts of global\u2026<\/div><\/div><\/article>
April 1, 2009<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips and Solutions – Visualizing Drift and Diffusion Current Densities<\/a><\/h3>
One of the most important features of TCAD simulation is that the TCAD tools encapsulate the physics of the processes or devices\u2026<\/div><\/div><\/article>
April 1, 2009<\/div>
Simulation Standard<\/div><\/div>

Simulating SiGe and Impurity Dependent Stress<\/a><\/h3>
The simulation of stress during device fabrication is becoming increasingly important and is often now deliberately introduced during fabrication to enhance device\u2026<\/div><\/div><\/article>
April 1, 2009<\/div>
Simulation Standard<\/div><\/div>

Physical 3D Single Event Upset Simulation of a SRAM Cell with VICTORY DEVICE and SmartSpice<\/a><\/h3>
VICTORY DEVICE simulation framework includes tools for 1D, 2D and 3D simulation of modern semiconductor technologies. VICTORY DEVICE implements a full tetrahedral\u2026<\/div><\/div><\/article>
April 1, 2009<\/div>
Simulation Standard<\/div><\/div>

Electrically Controlled Silicon-based Photonic Crystal Chromatic Dispersion Compensator with Ultra Low Power Consumption<\/a><\/h3>
We show full 3-Dimensional (3D) electrical and optical simulation of a tunable silicon-based Photonic Crystal (PhC) Chromatic Dispersion Compensator (CDC) with high\u2026<\/div><\/div><\/article>
April 1, 2009<\/div>
Simulation Standard<\/div><\/div>

SONOS\/SANOS Simulation in ATLAS<\/a><\/h3>
Semiconductor-Oxide-Nitride-Oxide-Semiconductor (SONOS) Non-Volatile memory structures can be simulated using ATLAS. The basic principle of these devices is the use of a charge\u2026<\/div><\/div><\/article>
January 1, 2009<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips and Solutions – Determining the CV Curve and Terminal Currents of a MOSFET<\/a><\/h3>
Q: How can I get a CV curve of a MOSFET? And how can I get the current on all terminals? A:\u2026<\/div><\/div><\/article>
January 1, 2009<\/div>
Simulation Standard<\/div><\/div>

Minimization of Well-Proximity Effect by Means of 2D and 3D Monte Carlo Simulation of Retrograde Well Implantation<\/a><\/h3>
The formation of deep p- and n- wells using high-energy implantation has become an integral part of CMOS technology process flow. The\u2026<\/div><\/div><\/article>
January 1, 2009<\/div>
Simulation Standard<\/div><\/div>

3D Simulation of Oxidation Induced Stress Using Cartesian Meshes with Adaptive Refinement<\/a><\/h3>
The formation of isolation trenches is one of the key process steps used in power device fabrication. Also the intensive scaling of\u2026<\/div><\/div><\/article>
January 1, 2009<\/div>
Simulation Standard<\/div><\/div>

3D Simulation of Ion Milling for Mass Storage Applications<\/a><\/h3>
The ion milling process is used extensively in the Hard Disc Drive industry, particularly in the manufacture of thin film magnetic heads.\u2026<\/div><\/div><\/article>
January 1, 2009<\/div>
Simulation Standard<\/div><\/div>

Self-Heating effect Simulation of GaN HFET Devices – 4H-SiC and Sapphire Substrate Comparison<\/a><\/h3>
GaN-based Hetero-Field Effect Transistors have been investigated in high power and high frequency electronics devices. However, such improved performance is still subject\u2026<\/div><\/div><\/article>
January 1, 2009<\/div>
Simulation Standard<\/div><\/div>

Modeling of GaInP\/GaAs DualJunction Solar Cells Including Tunnel Junction<\/a><\/h3>
This paper presents research efforts conducted at the IESUPM in the development of an accurate, physically-based solar cell model using the general-purpose\u2026<\/div><\/div><\/article>
November 1, 2007<\/div>
Simulation Standard<\/div><\/div>

Ballistic Quantum Transport in Nanoscale Transistors: a Non Equilibrium Green\u2019s Function Approach<\/a><\/h3>
Introduction As MOS field-effect transistors are scaled down to a nanometer regime, quantum effects in both transverse and transport directions start playing\u2026<\/div><\/div><\/article>
November 1, 2007<\/div>
Simulation Standard<\/div><\/div>

A Novel Approach to Three-Dimensional Semiconductor Process Simulation: Application to Thermal Oxidation<\/a><\/h3>
Abstract The paper presents a new approach to three-dimensional semiconductor process simulation that overcomes the problem of moving boundaries and mesh generation.\u2026<\/div><\/div><\/article>
August 1, 2007<\/div>
Simulation Standard<\/div><\/div>

Simulation of an Organic Photovoltaic Cell (OPC) Using Atlas<\/a><\/h3>
Introduction In recent years, the investigation of Organic Light Emitting Diodes (OLEDs) and photovoltaic devices based on small organic molecules and polymers\u2026<\/div><\/div><\/article>
August 1, 2007<\/div>
Simulation Standard<\/div><\/div>

Two-Dimensional Atlas Device Simulation of an Organic Light-Emitting Field-Effect Transistor Using a Heterostructure Inside the Transistor Channel<\/a><\/h3>
1. Introduction Organic semiconductors have been incorporated in a wide range of devices, including organic thin-film transistors (OTFTs) and circuits, organic solar\u2026<\/div><\/div><\/article>
May 1, 2007<\/div>
Simulation Standard<\/div><\/div>

Electrical Stress Degradation of Small-Grain Polysilicon Thin-Film Transistors<\/a><\/h3>
Abstract This paper is focused on the stability of n-channel laser-crystallized polysilicon thin-film transistors (TFTs) submitted to a hydrogenation process during the\u2026<\/div><\/div><\/article>
May 1, 2007<\/div>
Simulation Standard<\/div><\/div>

Trapping Effects in the Transient Response of AlGaN\/GaN HEMT Devices<\/a><\/h3>
In this paper, the transient analysis of an AlGaN\/GaN high-electron mobility transistor (HEMT) device is presented. Drain\u2013current dispersion effects are investigated when\u2026<\/div><\/div><\/article>
May 1, 2007<\/div>
Simulation Standard<\/div><\/div>

New Feature of Quantum Module: Schr\u00f6dinger-Poisson Solver for Nanowire Application<\/a><\/h3>
Introduction The trend toward ultra-short gate length MOSFET requires a more and more effective control of the channel by the gate leading\u2026<\/div><\/div><\/article>
February 1, 2007<\/div>
Simulation Standard<\/div><\/div>

How Can I significantly Reduce Circuit Parasitics Netlist Extraction Time?<\/a><\/h3>
How Can I significantly Reduce Circuit Parasitics Netlist Extraction Time?<\/div><\/div><\/article>
February 1, 2007<\/div>
Simulation Standard<\/div><\/div>

TCAD Modeling and Data of NOR Nanocrystal Memories<\/a><\/h3>
Introduction It is widely believed that the scaling of standard Flash devices will face in a near future several limitations, due to\u2026<\/div><\/div><\/article>
February 1, 2007<\/div>
Simulation Standard<\/div><\/div>

A Semi-Analytical Model for the Subthreshold Behavior of FinFLASH Structures<\/a><\/h3>
Abstract In this paper we present an original semi-analytical model for the subthreshold electrical behavior of complex 3D structures as the SOI\u2026<\/div><\/div><\/article>
November 1, 2006<\/div>
Simulation Standard<\/div><\/div>

Is it possible to calculate the resistance components of a MOSFET<\/a><\/h3>
Q.\u00a0Is it possible to calculate the resistance components of a MOSFET (i.e. channel resistance, epi resistance, substrate resistance etc.) as a function\u2026<\/div><\/div><\/article>
November 1, 2006<\/div>
Simulation Standard<\/div><\/div>

Design Rules and Trends for Dummy Metal Filling Using Exact, Clever and Stellar<\/a><\/h3>
Introduction The physical verification is becoming the most complex phase raised by the Deep SubMicron (DSM) technology. More than 50% of the\u2026<\/div><\/div><\/article>
November 1, 2006<\/div>
Simulation Standard<\/div><\/div>

Advanced Quantum Effects Simulation in Atlas<\/a><\/h3>
Introduction The trend toward smaller MOSFET devices with thinner gate oxide and greater doping is resulting in the increased importance of quantum\u2026<\/div><\/div><\/article>
November 1, 2006<\/div>
Simulation Standard<\/div><\/div>

TCAD Simulation of a SONOS Device with Silvaco\u2019s new FNONOS Model<\/a><\/h3>
Introduction Erasable programmable read-only memory (EPROM) devices include amongst others, floating gate technology and SONOS (Polysilicon-Oxide-Nitride-Silicon) technology. Floating gate technology involves charge\u2026<\/div><\/div><\/article>
August 1, 2006<\/div>
Simulation Standard<\/div><\/div>

How to obtain a stable grid and smooth doping profile in non-planar a-Si TFT using Athena\/Elite?<\/a><\/h3>
How to obtain a stable grid and smooth doping profile in non-planar a-Si TFT using\u00a0Athena\/Elite?<\/div><\/div><\/article>
August 1, 2006<\/div>
Simulation Standard<\/div><\/div>

Three Dimensional Electro-Thermodynamic Analysis for GaN Light Emitting Diodes<\/a><\/h3>
Abstract Improvement in temperature characteristics of GaN LEDs is important for realizing reliable devices operating at high temperatures. In this article, the\u2026<\/div><\/div><\/article>
August 1, 2006<\/div>
Simulation Standard<\/div><\/div>

Accurate Spice Netlist Extraction in Stellar Using New Substrate Partition Feature<\/a><\/h3>
Introduction By default\u00a0STELLAR\u00a0calculates the capacitances between interconnect lines and the whole substrate. In certain conditions it may lead to some inaccuracies. For\u2026<\/div><\/div><\/article>
August 1, 2006<\/div>
Simulation Standard<\/div><\/div>

Atlas Device Simulation of Amorphous Oxide Semiconductor Thin-Film Transistors<\/a><\/h3>
1. Introduction Amorphous oxide semiconductor materials have attracted much attention as key components of TFTs for flexible electronics [1]. The advantages of\u2026<\/div><\/div><\/article>
August 1, 2006<\/div>
Simulation Standard<\/div><\/div>

Simulating the Source of Polarization Charge in AlGaN\/GaN HFETs<\/a><\/h3>
Polarization-induced charges at the AlGaN\/GaN interface of heterojunction field-effect transistors (HFETs) create a high density, two-dimensional electron gas (2DEG) in the channel.\u2026<\/div><\/div><\/article>
May 1, 2006<\/div>
Simulation Standard<\/div><\/div>

Interconnect Parasitic Extraction of BiCMOS Cell Using Silvaco Clever<\/a><\/h3>
Interconnect parasitic effects play a very important role in modern integrated circuit design, especially for digital circuit. This article presents how a\u2026<\/div><\/div><\/article>
May 1, 2006<\/div>
Simulation Standard<\/div><\/div>

Evaluating of the Avalanche Failure of Power MOSFETs using Atlas<\/a><\/h3>
Introduction Power MOSFETs are widely used with an inductive load for S\/W power supplies, DC-DC converters, and so on. But due to\u2026<\/div><\/div><\/article>
May 1, 2006<\/div>
Simulation Standard<\/div><\/div>

Comparison of 3-Dimensional Quantum Effects in Nano Devices Using the Atlas 3D BQP Model<\/a><\/h3>
Introduction With the MOSFET gate lengths scaling down to sub-20nms many kinds of devices have been proposed and researched such as double-gate,\u2026<\/div><\/div><\/article>
May 1, 2006<\/div>
Simulation Standard<\/div><\/div>

Enhanced Silicon Light Emission Intensity with Multiple SiGe Quantum Well Structure<\/a><\/h3>
Abstract The measured I-V curve from a ten period Si\/SiGe MQW pin LED fabricated using a UHVCVD system is compared with\u00a0ATLAS\u00a0simulation results.\u2026<\/div><\/div><\/article>
February 1, 2006<\/div>
Simulation Standard<\/div><\/div>

Multi-layer Organic Light Emitting Diode Simulation<\/a><\/h3>
A conventional 2 layer organic light emitting diode consists of a Hole Ttransport Layer (HTL) and an electron transport layer (ETL). A\u2026<\/div><\/div><\/article>
February 1, 2006<\/div>
Simulation Standard<\/div><\/div>

Crosstalk Between Pixels of Organic Photo-Voltaic Devices<\/a><\/h3>
For various technological reasons, LEDs and as well as photo-voltaic devices frequently use PEDOT:PSS on top of ITO contacts as a hole\u2026<\/div><\/div><\/article>
February 1, 2006<\/div>
Simulation Standard<\/div><\/div>

Athena\/Optolith Simulation of Proximity Lithography<\/a><\/h3>
Photolithography simulation is a very important part of TCAD. Accurate and predictive lithography simulation saves time and money spent on development and\u2026<\/div><\/div><\/article>
February 1, 2006<\/div>
Simulation Standard<\/div><\/div>

Inductance Optimization using 3D Field Solver based on Design Of Experiment Approach<\/a><\/h3>
A new 3D electromagnetic simulator coupled with a statistical analysis, for inductance loop optimization is presented. It allows RF designers to easily\u2026<\/div><\/div><\/article>
November 1, 2005<\/div>
Simulation Standard<\/div><\/div>

How can I create a non planar structure using III-V materials for Device Analysis<\/a><\/h3>
How can I create a non planar structure using III-V materials for Device Analysis when the materials I want to use are\u2026<\/div><\/div><\/article>
November 1, 2005<\/div>
Simulation Standard<\/div><\/div>

Numerical Analysis of GaInP Solar Cells: Toward Advanced Photovoltaic Devices Modeling<\/a><\/h3>
Simulation capacities of GaInP solar cells were studied with a special emphasis on material and structural parameters. The comparison between experimental and\u2026<\/div><\/div><\/article>
November 1, 2005<\/div>
Simulation Standard<\/div><\/div>

Simulation and Characterization of High-Frequency Performances of Advanced MIM Capacitors<\/a><\/h3>
Abstract: High-frequency simulations and characterizations of advanced metal-insulator-metal (MIM) capacitors with ultra thin 32 nm PECVD Si3N4\u00a0dielectric are presented. The frequency dependent\u2026<\/div><\/div><\/article>
August 1, 2005<\/div>
Simulation Standard<\/div><\/div>

How can I create a Design Of Experiments (DOE) using DeckBuild with one or more variables<\/a><\/h3>
How can I create a Design Of Experiments (DOE) using\u00a0DeckBuild\u00a0with one or more variables specified in a single input file when I\u2026<\/div><\/div><\/article>
August 1, 2005<\/div>
Simulation Standard<\/div><\/div>

Process Flow Simulation and Manufacture of Variable RF MEMS Capacitors<\/a><\/h3>
Introduction The application of microelectromechanical systems (MEMS) to radio-frequency (RF)\/microwave systems is on the verge of revolutionizing wireless communications, mainly in the\u2026<\/div><\/div><\/article>
August 1, 2005<\/div>
Simulation Standard<\/div><\/div>

Gate Charging Simulation Using Atlas\/MixedMode<\/a><\/h3>
Introduction In modern power devices, the total power loss comprises both a conductive power loss component and a capacitive loss component. As\u2026<\/div><\/div><\/article>
August 1, 2005<\/div>
Simulation Standard<\/div><\/div>

Using Athena Monte Carlo Module for Ion Implantation Simulation in Silicon Carbides<\/a><\/h3>
Introduction The Monte Carlo Implantation Module of\u00a0ATHENA\u00a0has proved to be a very accurate tool for simulation of various implantation processes. In this\u2026<\/div><\/div><\/article>
June 1, 2005<\/div>
Simulation Standard<\/div><\/div>

Is there a way to turn-off all of the generated layers<\/a><\/h3>
Is there a way to turn-off all of the generated layers so that the layout modifications can be done without them cluttering\u2026<\/div><\/div><\/article>
June 1, 2005<\/div>
Simulation Standard<\/div><\/div>

Expert\u2019s Netlist Driven Layout<\/a><\/h3>
Expert\u00a0features a powerful Netlist Driven Layout (NDL) function to assist the user in creating a layout. It increases the productivity of layout\u2026<\/div><\/div><\/article>
June 1, 2005<\/div>
Simulation Standard<\/div><\/div>

Expert Parametric Wires<\/a><\/h3>
Expert\u00a0Parametric Wire (Pwire) is a complex group of objects containing, a single wire named master wire, any number of subparts such as\u2026<\/div><\/div><\/article>
May 1, 2005<\/div>
Simulation Standard<\/div><\/div>

I am currently using ATLAS\/ Blaze to model the electrical properties of an LED device<\/a><\/h3>
I am currently using\u00a0ATLAS\/\u00a0Blaze\u00a0to model the electrical properties of an LED device that I am investigating. Is it possible to examine the\u2026<\/div><\/div><\/article>
May 1, 2005<\/div>
Simulation Standard<\/div><\/div>

Simulating the Device Characteristics of MEH-PPV Polymer Light Emitting Diodes Using Atlas<\/a><\/h3>
Organic light emitting diodes (OLEDs) are attracting great interest in the display technology industry due to their promising low cost large area\u2026<\/div><\/div><\/article>
May 1, 2005<\/div>
Simulation Standard<\/div><\/div>

A Comprehensive Solution for Simulating Ultra-Shallow Junctions: From High Dose\/Low Energy Implant to Diffusion Annealing<\/a><\/h3>
The persistent semiconductor technology trend of shrinking down device size requires development of veryaggressive technological setups consisting in high dose\/low energy implants,\u2026<\/div><\/div><\/article>
March 1, 2005<\/div>
Simulation Standard<\/div><\/div>

Expert: Wiring<\/a><\/h3>
The wiring tool in\u00a0Expert\u00a0automatically creates the shortest wire connecting two points specified by the user. The created wire goes around any existing\u2026<\/div><\/div><\/article>
March 1, 2005<\/div>
Simulation Standard<\/div><\/div>

I have to send copies of my project layout to different members of my group<\/a><\/h3>
Q.\u00a0I have to send copies of my project layout to different members of my group, but they need to see only specific\u2026<\/div><\/div><\/article>
March 1, 2005<\/div>
Simulation Standard<\/div><\/div>

Expert: Layout Versus Layout (LVL) Comparison<\/a><\/h3>
Introduction The functionality Silvaco\u2019s Layou Editor,\u00a0Expert, has recently been expanded with the new feature called Layout Versus Layout comparison (LVL). LVL is\u2026<\/div><\/div><\/article>
March 1, 2005<\/div>
Simulation Standard<\/div><\/div>

New Parasitic Capacitance Modeling in Hipex-C<\/a><\/h3>
In deep submicron technology, conduction layers have widths much smaller than their thicknesses (see Figure 1). This makes edge parasitic capacitance effects\u2026<\/div><\/div><\/article>
March 1, 2005<\/div>
Simulation Standard<\/div><\/div>

Capacitance Coupling Calculation of IPS mode TFT-LCD Using Clever<\/a><\/h3>
The increasing demand of the TFT-LCD industry has lead to a rapid growth in display size and resolution. The higher cell packing\u2026<\/div><\/div><\/article>
February 1, 2005<\/div>
Simulation Standard<\/div><\/div>

Can Athena get the STRESS in Compound Advanced material?<\/a><\/h3>
Q:\u00a0Can\u00a0ATHENA\u00a0get the STRESS in Compound Advanced material? A:\u00a0The\u00a0ATHENA\u00a0STRESS command has been augmented to allow the 2 Dimensional stress distribution. To get the\u2026<\/div><\/div><\/article>
February 1, 2005<\/div>
Simulation Standard<\/div><\/div>

Simulating Selective and Non-Selective Epitaxy Over Oxide Isolated Regions Using Athena<\/a><\/h3>
In certain cases, most notably in modern bipolar and SiGe HBT structures, epitaxial steps are performed after the oxide isolation structures have\u2026<\/div><\/div><\/article>
February 1, 2005<\/div>
Simulation Standard<\/div><\/div>

Process and Device Simulation of Field Emission Microtrides<\/a><\/h3>
One of the most beneficial merits of computer-based experiment using TCAD lies in its capability of a total simulation of the target\u2026<\/div><\/div><\/article>
February 1, 2005<\/div>
Simulation Standard<\/div><\/div>

Pending Issues in the Modeling of Concentrator Solar Cells<\/a><\/h3>
The modelling of concentrator solar cells for real conditions of operation inside optical concentrators is a subject almost untreated. Consequently, this work\u2026<\/div><\/div><\/article>
December 1, 2004<\/div>
Simulation Standard<\/div><\/div>

How can I view a Foundry DRC run in Expert?<\/a><\/h3>
Q: How can I view a Foundry DRC run in Expert? A: Before a Foundry will start creating the masks to fabricate\u2026<\/div><\/div><\/article>
December 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Using Expert\u2019s Pcell Feature to Generate Complex Shaped Layers<\/a><\/h3>
One of the strengths of\u00a0Expert\u00a0is to generate complex shaped layers such as spiral inductors, parabolic waveguides, etc. For the case of the\u2026<\/div><\/div><\/article>
December 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Cross-Sectional Viewer<\/a><\/h3>
Cross-Sectional Viewer is a tool in the\u00a0Expert\u00a0layout editor that simulates the cross-sections of ICs along an arbitrary drawn cut-line on the layout.\u2026<\/div><\/div><\/article>
November 1, 2004<\/div>
Simulation Standard<\/div><\/div>

How do you perform a lift off procedure in ATHENA?<\/a><\/h3>
A common technique for creating metal contacts is one known as a lift off. When performing a lift off process step, in\u2026<\/div><\/div><\/article>
November 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Transient Simulations of Edge Emitting Fabry-Perot InP\/InGaAsP Laser Diode Using Silvaco TCAD Tools<\/a><\/h3>
In this communication we present a brief description of our initial results of transient simulation of InP\/InGaAsP Fabry-Perot edge emitting laser diode\u2026<\/div><\/div><\/article>
November 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Practice of LPE Rule File Generation by Exact<\/a><\/h3>
This article will show how you can create LPE rule files using EXACT\u2019s LISA scripting functionality. We will concentrate on generating a\u2026<\/div><\/div><\/article>
November 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Two-Dimensional Device Simulation of the InGaAs\/InP Avalanche Photodiodes<\/a><\/h3>
The high gain, and high gain-bandwidth product of the avalanche photodiodes is one of the key device for the long distance optical\u2026<\/div><\/div><\/article>
November 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Resistor and Capacitor L\/W Parameters in LVS Comparison<\/a><\/h3>
In the design of VLSI circuits the situations occur very often when a single schematic device is implemented in the layout by\u2026<\/div><\/div><\/article>
October 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Fast and Accurate Simulation of the Steady-State of Voltage Controlled Oscillators with SmartSpice-RF<\/a><\/h3>
A novel simulation method of the steady-state of oscillators, based on Harmonic Balance (HB), is presented. A comparison with regular transient simulations\u2026<\/div><\/div><\/article>
October 1, 2004<\/div>
Simulation Standard<\/div><\/div>

A Sophisticated Verilog-A Debugger<\/a><\/h3>
During the elaboration of a\u00a0Verilog-A\u00a0model, debugging a module can be very useful for detecting non-physical behavior or fine-tuning the model. The SILVACO\u00a0Verilog-A\u00a0debugger\u2026<\/div><\/div><\/article>
October 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Noise Simulations<\/a><\/h3>
If the MOS model file has the parameters: noia, noib, noic, Af, Kf and nlev=0 will\u00a0SmartSpice\u00a0ignore the BSIM III noise parameters (noia,\u2026<\/div><\/div><\/article>
September 1, 2004<\/div>
Simulation Standard<\/div><\/div>

EDIF Conversion Flow on Gateway<\/a><\/h3>
EDIF has been a vital part of the Electronic Design Automation (EDA) industry for many years and Gateway allows users to convert\u2026<\/div><\/div><\/article>
September 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Hipex-CRC Parasitic RC-Network Reducer<\/a><\/h3>
Design of large scale chips requires precise knowledge of interconnect delays. However, detailed analysis of interconnects may quickly become computationally too expensive\u2026<\/div><\/div><\/article>
September 1, 2004<\/div>
Simulation Standard<\/div><\/div>

SET Accurate Compact Model for SET-MOSFET Hybrid Circuit Simulation<\/a><\/h3>
Single-Electron Transistors (SETs) [1][2] are attractive candidates for post-CMOS VLSI ICs. Accurate models are also required in order to efficiently design SET\u2026<\/div><\/div><\/article>
September 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Generic Devices – The New HIPEX-NET Feature for Extraction of Custom Devices<\/a><\/h3>
Hipex-NET\u00a0is SILVACO\u2019s powerfull hierarchical layout netlist extractor. Built-in extracting rules permit to make fast and accurate parameter extraction for basic set of\u2026<\/div><\/div><\/article>
September 1, 2004<\/div>
Simulation Standard<\/div><\/div>

How can I become a more efficient user of Expert?<\/a><\/h3>
How can I become a more efficient user of\u00a0Expert?<\/div><\/div><\/article>
August 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Electrostatic Effect of Localized Charge in Dual Bit Memory Cells with DiscreteTraps<\/a><\/h3>
In this paper the electrostatic impact of Channel Hot Electron (CHE) injection in discrete-trap memories is quantitatively addressed. The dual bit behavior\u2026<\/div><\/div><\/article>
August 1, 2004<\/div>
Simulation Standard<\/div><\/div>

A New Efficient Quantum Method: The Bohm Quantum Potential Model<\/a><\/h3>
This article presents a new approach to model the quantum confinement of carriers in MOSFET or heterostructure. SILVACO has already included in\u2026<\/div><\/div><\/article>
August 1, 2004<\/div>
Simulation Standard<\/div><\/div>

The subject of how to use the EXTRACT statement in DeckBuild often arises<\/a><\/h3>
The subject of how to use the EXTRACT statement in\u00a0DeckBuild\u00a0often arises. The EXTRACT statement is a very useful tool for analysing data\u2026<\/div><\/div><\/article>
August 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Simulating Selective and Non-Selective Epitaxy over Oxide Isolated Regions Using Athena<\/a><\/h3>
In certain cases, most notably in modern bipolar and SiGe HBT structures, epitaxial steps are performed after the oxide isolation structures have\u2026<\/div><\/div><\/article>
July 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Silvaco\u2019s RFIC Design Suite<\/a><\/h3>
This article focuses on the use of Silvaco\u2019s RFIC Design Suite including PDK,\u00a0SmartSpice-RF, and\u00a0Gateway.<\/div><\/div><\/article>
July 1, 2004<\/div>
Simulation Standard<\/div><\/div>

HiSIM-1.2 Parameter Extraction with the Revised UTMOST-III Local Optimization Strategies<\/a><\/h3>
HiSIM-1.2 parameter extraction methodology was discussed in detail in a previous issue of Silvaco Simulation Standard [1]. This article is meant to\u2026<\/div><\/div><\/article>
July 1, 2004<\/div>
Simulation Standard<\/div><\/div>

A Family Portrait of the BSIM Models<\/a><\/h3>
1. Introduction BSIM1, the first model of the BSIM series was released about ten years ago. Some major improvements have been made\u2026<\/div><\/div><\/article>
July 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Customers are starting to use 64bit machines with large hard drives and Gigs of RAM<\/a><\/h3>
Customers are starting to use 64bit machines with large hard drives and Gigs of RAM and tend to forget the limitations imposed\u2026<\/div><\/div><\/article>
June 1, 2004<\/div>
Simulation Standard<\/div><\/div>

New Features in Expert Node Probing<\/a><\/h3>
Expert\u2019s Node Probing is powerful tool for inspection of netlist components on layout. It is designed for highlighting layout objects electrically connected\u2026<\/div><\/div><\/article>
June 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Parasitic Capacitance Extraction with Hipex and Exact<\/a><\/h3>
Overview To extract parasitic capacitances from a circuit layout, you need to perform the following steps:<\/div><\/div><\/article>
June 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Expert Layout Editor \u2013 New Commands Focus On Easier Operation<\/a><\/h3>
Expert\u00a0layout editor version 4.0.1R has several new commands and functions released together with the new Qt GUI interface. Most of them are\u2026<\/div><\/div><\/article>
June 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Every time I create a new project or library, an empty cell with the same name is created in my project<\/a><\/h3>
Q. Every time I create a new project or library, an empty cell with the same name is created in my project.\u2026<\/div><\/div><\/article>
May 1, 2004<\/div>
Simulation Standard<\/div><\/div>

STELLAR \u2013 Process Based Parasitics Capacitance Extraction on Large Custom Cells<\/a><\/h3>
SILVACO has recently released a new suite of interconnect analysis tools to meet the demands of state of the art cell, circuit\u2026<\/div><\/div><\/article>
May 1, 2004<\/div>
Simulation Standard<\/div><\/div>

LPE Optimization with Clever\/Hipex\/Exact Linkage Methodology<\/a><\/h3>
On the cutting edge of LSI design, the accuracy of Layout Parasitic Extraction (LPE) tools is a critical issue to miniaturized LSI\u2026<\/div><\/div><\/article>
May 1, 2004<\/div>
Simulation Standard<\/div><\/div>

When solving for the static CV curve for a MOS capacitor, due to the absence of current carriers<\/a><\/h3>
When solving for the static CV curve for a MOS capacitor, due to the absence of current carriers, convergence can be a\u2026<\/div><\/div><\/article>
April 1, 2004<\/div>
Simulation Standard<\/div><\/div>

IBIS Models Now Supported in SmartSpice<\/a><\/h3>
Expert\u00a0Parametric Wire (Pwire) is a complex group of objects containing, a single wire named master wire, any number of subparts such as\u2026<\/div><\/div><\/article>
April 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Extraction of SPICE Model Parameters from Atlas Device Simulation Using Utmost<\/a><\/h3>
Many users would like to extract SPICE models from their process and device simulation using Athena and Atlas to be used in\u2026<\/div><\/div><\/article>
April 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Array Copying – Alignment from Specified Instance Number<\/a><\/h3>
For LCD and Memory designs, Array Copy function on Gateway is conveniently used. Users may want to align instances from specified instance\u2026<\/div><\/div><\/article>
March 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Hierarchical Layout versus Schematic<\/a><\/h3>
A new Hierarchical Layout versus Schematic (HLVS) system that provides significant improvement in verification of huge circuits is described. Other of LVS\u2026<\/div><\/div><\/article>
March 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Design of Optimal Spiral Inductors in Expert<\/a><\/h3>
Introduction One of the key components in many RF ICs applications is the inductor. It is very important that the inductor has\u2026<\/div><\/div><\/article>
March 1, 2004<\/div>
Simulation Standard<\/div><\/div>

When I do an extract, the generated layers are present in the layout.<\/a><\/h3>
Q:\u00a0When I do an extract, the generated layers are present in the layout. If I need to do layout modifications I find\u2026<\/div><\/div><\/article>
March 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Resistance Calculation Approach in Hipex-NET<\/a><\/h3>
Hipex-NET\u00a0uses two techniques to calculate resistor values. First method of resistance extraction, which is usual for full chip netlist extractors and uses\u2026<\/div><\/div><\/article>
March 1, 2004<\/div>
Simulation Standard<\/div><\/div>

TCAD Simulation of a Dual Band Monolithic HgCdTe Infrared Photodetector<\/a><\/h3>
Introduction Mercury cadmium telluride (HgCdTe) is a semiconductor material whose material properties are adjustable through altering its constitutive molar fractions. HgCdTe has\u2026<\/div><\/div><\/article>
February 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Mocasim – A Versatile Monte Carlo Simulator for III-Nitride Transport Properties<\/a><\/h3>
III-Nitrides have recently attracted attention as a promising material class for high-power, high-frequency microelectronic applications at elevated temperatures. They possess large band\u2026<\/div><\/div><\/article>
February 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Schr\u00f6dinger Approach and Density Gradient Model for Quantum Effects Modeling<\/a><\/h3>
We describe here two approaches to model the quantum effects that can no more be neglected in actual and future devices. These\u2026<\/div><\/div><\/article>
February 1, 2004<\/div>
Simulation Standard<\/div><\/div>

How can I use the EXTRACT commands to find the depletion widths in my MOSFET at different drain biases?<\/a><\/h3>
To illustrate the use of this statement to find depletion widths we have used the standard MOSFET example mos1ex01.in to first create\u2026<\/div><\/div><\/article>
February 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Instructional Approach to Writing Parasitic Capacitance Rules Files Using Exact<\/a><\/h3>
1. Introduction The\u00a0Exact\u00a0analysis stage extracts the user-required information necessary for the respective parasitic capacitances by probing the\u00a0Exact\u00a0database. This is performed via script\u2026<\/div><\/div><\/article>
February 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Simulation of Silica Microlenslet Formation by Etch and Reflow Using Elite and SSuprem4<\/a><\/h3>
Introduction In response to high demand, device designers are developing silica microlenslets that offer efficient coupling between optical fiber bundles and arrays\u2026<\/div><\/div><\/article>
January 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Remote ALTER processing<\/a><\/h3>
A new parallelization method has been implemented into\u00a0SmartSpice. Now .ALTERs can be destributed not only over several CPUs (by using -P option),\u2026<\/div><\/div><\/article>
January 1, 2004<\/div>
Simulation Standard<\/div><\/div>

New SmartLIb Library of Models<\/a><\/h3>
In all previous versions of\u00a0SmartSpice\u00a0the model code (BSIM, diode etc.) was included in the one executable (SmartSpice\u00a0). This means any updates to\u2026<\/div><\/div><\/article>
January 1, 2004<\/div>
Simulation Standard<\/div><\/div>

BSIM4 Model Verilog-A Implementation<\/a><\/h3>
The Verilog-A hardware description language opens many areas to SPICE users in the field of compact models, allowing manufacturers and universities to\u2026<\/div><\/div><\/article>
January 1, 2004<\/div>
Simulation Standard<\/div><\/div>

Stress Effect Model in BSIM3v3 Model<\/a><\/h3>
Stress effect models are now implemented in major models such as BSIM4 or HiSIM. The need for evermore accurate models with a\u2026<\/div><\/div><\/article>
January 1, 2004<\/div>
Simulation Standard<\/div><\/div>

New Philips MOS20 LDMOS Model in SmartSpice<\/a><\/h3>
Philips MOS20 was released in January 2004. Its purpose is to provide a high-voltage compact model to describe both operation of the\u2026<\/div><\/div><\/article>
December 4, 2003<\/div>
Simulation Standard<\/div><\/div>

Sometimes I have problem to skip cells when importing cells<\/a><\/h3>
Q:\u00a0Sometimes I have problem to skip cells when importing cells with the same names from reference library. Once we skip one cell,\u2026<\/div><\/div><\/article>
December 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Guardian DRC vs. Other DRC Systems, I<\/a><\/h3>
1. Introduction This article begins a series of articles that describe the compatibility of\u00a0Guardian\u00a0DRC system[1] in terms of functionality: command set, syntax\u2026<\/div><\/div><\/article>
December 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Schematic Driven Layout<\/a><\/h3>
Expert\u00a0schematic driven layout (SDL) is a CAD tool which increases the productivity of layout design by automating cell generation and providing visual\u2026<\/div><\/div><\/article>
December 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Interactive P-cell Generation<\/a><\/h3>
1. Abstract Parameterized cells (P-cells) significantly increase the productivity of layout designers. Silvaco International\u2019s tool\u00a0Expert\u00a0has been designed to aid layout designers through\u2026<\/div><\/div><\/article>
November 4, 2003<\/div>
Simulation Standard<\/div><\/div>

Interconnect Parasitic Accuracy & Speed Improvements in New CLEVER Release<\/a><\/h3>
Introduction This article introduces the new features and numerical schema implemented in the most recent release of Clever from Silvaco. In this\u2026<\/div><\/div><\/article>
November 4, 2003<\/div>
Simulation Standard<\/div><\/div>

Is there a way to automatically specify mesh spacing in ATHENA?<\/a><\/h3>
Q.\u00a0Is there a way to automatically specify mesh spacing in\u00a0ATHENA? A.\u00a0Yes, there are three ways to automatically specify grid spacing. The most\u2026<\/div><\/div><\/article>
November 2, 2003<\/div>
Simulation Standard<\/div><\/div>

Topography Simulation of Trench Etch Using Monte Carlo Plasma Etch Model with Polymer Re-deposition<\/a><\/h3>
1. Introduction The topography simulation module,\u00a0Elite\u00a0has constantly been improved in order to simulate advanced processes, which are becoming more complex with device\u2026<\/div><\/div><\/article>
November 1, 2003<\/div>
Simulation Standard<\/div><\/div>

TCAD Simulation of a Polysilicon Thin Film Transistor For Active Matrix Liquid Crystal Displays<\/a><\/h3>
Polysilicon thin film transistors are attractive as active devices in driver circuits of highly integrated active-matrix liquid crystal displays (AMLCDs) and as\u2026<\/div><\/div><\/article>
October 1, 2003<\/div>
Simulation Standard<\/div><\/div>

IBIS Models in SmartSpice<\/a><\/h3>
The Input\/Output Buffer Information Specification (IBIS) is a standard for electronic behavioral models based on I\/V and V\/T curve data. It is\u2026<\/div><\/div><\/article>
October 1, 2003<\/div>
Simulation Standard<\/div><\/div>

New Features in SmartSpice 2.3.4.C<\/a><\/h3>
A powerful new feature \u201cStop-Continue\u201d has been added to SmartSpice to allow the user to suspend a transient simulation and investigate the\u2026<\/div><\/div><\/article>
October 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Spectre\u00ae Replacement in the Cadence Flow<\/a><\/h3>
Silvaco has always supported the Solaris based Cadence design environment for seemless SmartSpice integration. To accommodate new customer demands to support the\u2026<\/div><\/div><\/article>
October 1, 2003<\/div>
Simulation Standard<\/div><\/div>

New Functionality \u2013 BUS notation in SmartSpice<\/a><\/h3>
A new notation has been introduced into SmartSpice to allow a compact expression of a multiple bit wire buss to be used.\u2026<\/div><\/div><\/article>
September 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Role of Netlist Extraction in Process Design Kits<\/a><\/h3>
Netlist extraction and the quality of netlist extraction is becoming of increasing concern for integrated circuit design flow. As circuits become more\u2026<\/div><\/div><\/article>
September 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Parasitic Resistor Extraction with HIPEX-R<\/a><\/h3>
HIPEX-R is part of HIPEX software package for physical verification of multimillion transistor designs. It is a hierarchical full chip parasitic resistance\u2026<\/div><\/div><\/article>
September 1, 2003<\/div>
Simulation Standard<\/div><\/div>

HIPEX-Net: New SILVACO Full-Chip LPE Tool vs. Maverick<\/a><\/h3>
SILVACO is releasing its new layout parameter extractor: HIPEX-NET. The new tool will replace Silvaco\u2019s Maverick, which is a part of Guardian\u2026<\/div><\/div><\/article>
September 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Measurement of Spacing Checks in Guardian DRC<\/a><\/h3>
In previous versions of Guardian DRC there were only two ways of measuring the distance between two segments: the ordinary, Euclidean metric,\u2026<\/div><\/div><\/article>
September 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Highlighting Two Nodes in the Expert Layout Editor and Other Tips<\/a><\/h3>
Q: I would like to highlight two nodes at the same time in Expert. I currently use Verification->Node Probing->Pick Node to highlight\u2026<\/div><\/div><\/article>
August 1, 2003<\/div>
Simulation Standard<\/div><\/div>

The Effect of Carrier Spilling on Spreading Resistance Profiling (SRP) Accuracy<\/a><\/h3>
Spreading Resistance Profiling (SRP) retains its popularity in the semiconductor industry by an inexpensive means of capturing dopant profile information. However, device\u2026<\/div><\/div><\/article>
August 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Eye Diagram for a Direct Modulated Semiconductor Laser in ATLAS<\/a><\/h3>
An eye diagram is a convenient way to visualise how the waveforms used to send multiple bits of data can potentially lead\u2026<\/div><\/div><\/article>
August 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Analysis of Light Power Dependence on the Leakage Current in a Buried Hetero- Structure p-InP Semiconductor Laser<\/a><\/h3>
An effective device structure for reducing leakage current in BH laser diodes with semiin-sulation doped Fe in InP blocking layers has been\u2026<\/div><\/div><\/article>
August 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Generation of III-Nitride Transport Parameters with Mocasim<\/a><\/h3>
Mocasim is an advanced three-valley Monte Carlo simulator designed to generate the transport parameters used in Silvaco\u2019s physical device simulators. It accurately\u2026<\/div><\/div><\/article>
August 1, 2003<\/div>
Simulation Standard<\/div><\/div>

EXACT Worksheet Utility to View Variables and Data<\/a><\/h3>
Q: EXACT has powerful scripting utilities for manipulating the final capacitance data and variables but is there an easier graphical front end\u2026<\/div><\/div><\/article>
July 1, 2003<\/div>
Simulation Standard<\/div><\/div>

HiSIM V1.2 Model Parameter Extraction with UTMOST-III<\/a><\/h3>
HiSIM (Hiroshima university STARC IGFET Model) is one of the surface potential based Spice models [1], [2] and pioneered the iterative approach\u2026<\/div><\/div><\/article>
July 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Shallow-Trench-Isolation (STI) Effects in BSIM4 and HiSIM MOSFET Models in SmartSpice & UTMOST-III<\/a><\/h3>
There are several ways to account for the effect of STI-induced stress in standard compact models. The purpose of this article is\u2026<\/div><\/div><\/article>
July 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Behavioral Modeling of PLL Using Verilog-A with SmartSpice<\/a><\/h3>
In this article, we describe practical behavioral modeling for highly non-linear circuits using Verilog-A, which is analog extension of Verilog-AMS. At first,\u2026<\/div><\/div><\/article>
July 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Using Binned Device Models with SmartSpice<\/a><\/h3>
Q. My simulation fails because SmartSpice cannot find a binned model, what does this mean?<\/div><\/div><\/article>
June 1, 2003<\/div>
Simulation Standard<\/div><\/div>

HIPEX-Net: Hierarchical Layout Extractor for Expert Editor<\/a><\/h3>
HIPEX-Net is a hierarchical layout extractor. It can create both hierarchical and flat SPICE formatted netlists of the extracted layout. HIPEX-Net also\u2026<\/div><\/div><\/article>
June 1, 2003<\/div>
Simulation Standard<\/div><\/div>

\u201cShortest Path\u201d Option for Flight Line Style (Net Bar)<\/a><\/h3>
There is the recent improvement in Expert Layout Editor, the \u201cShortest path\u201d option was added to Flight line styles (Net Bar). This\u2026<\/div><\/div><\/article>
June 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Expert Layout Editor Recent Improvements: Over-the-Point Drawing of Orthogonal Shapes<\/a><\/h3>
This article presents an overview of new features added to Silvaco's Expert layout editor. Silvaco has taken a careful look at the\u2026<\/div><\/div><\/article>
June 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Guardian DRC Edge Layer Operations<\/a><\/h3>
Recent versions of Guardian DRC introduce operations that involve edge layers, either on input or on output.\u00a0An edge layer is a layer\u2026<\/div><\/div><\/article>
June 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Guardian LVS: New Platform-Independent GUI<\/a><\/h3>
We introduce a platform-independent version of Guardian LVS. An important feature of any tool is its capability to operate on various platforms\u2026<\/div><\/div><\/article>
June 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Counting Instances in an Expert Editor Layout<\/a><\/h3>
Q: I have some trouble counting the number of in-stances in a layout using Expert. I have tried to use the Chip\u2026<\/div><\/div><\/article>
May 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Low Voltage Super Junction MOSFET Simulation and Experimentation<\/a><\/h3>
The application of Super Junction concepts to a low voltage power MOSFET is investigated. The body junction is modified with the addition\u2026<\/div><\/div><\/article>
May 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Using The Statistical Sampling Feature in the BCA Monte Carlo Implant Simulator<\/a><\/h3>
Silvaco\u2019s Binary Collision Approximation (BCA) Monte- Carlo Implantation simulator closely replicates the physics of implantation by individually tracking implanted ions and their\u2026<\/div><\/div><\/article>
May 1, 2003<\/div>
Simulation Standard<\/div><\/div>

A Comparison Between Classical Full Chip Extraction and Field Solver Parasitic Extraction<\/a><\/h3>
This article will present two different ways to extract parasitics from an IC design: first using a full chip extraction tool HIPEX-RC\u2026<\/div><\/div><\/article>
May 1, 2003<\/div>
Simulation Standard<\/div><\/div>

ATLAS Simulation of an SEU Event in 2D<\/a><\/h3>
Q: Can ATLAS simulate an SEU event in 2D? To simulate a single event upset (SEU) is inherently a 3D problem because\u2026<\/div><\/div><\/article>
April 1, 2003<\/div>
Simulation Standard<\/div><\/div>

RPI VCSEL Model Released in SmartSpice<\/a><\/h3>
RPI VCSEL model was developed by Professor Michael Shur and his team from the Rensselaer Polytechnic Institute (RPI) [1]. A release of\u2026<\/div><\/div><\/article>
April 1, 2003<\/div>
Simulation Standard<\/div><\/div>

BSIM3v3 Model Verilog-A Implementation<\/a><\/h3>
Berkeley University BSIM3v3 model is the industry-standard, physics-based, deep-submicron MOSFET model for digital and analog circuit designs. This makes BSIM3v3 model a\u2026<\/div><\/div><\/article>
April 1, 2003<\/div>
Simulation Standard<\/div><\/div>

New Device Model Card Approach<\/a><\/h3>
Normally a single active device model is extracted to cover a range of device geometries and temperature. Sometimes this single scalable model\u2026<\/div><\/div><\/article>
April 1, 2003<\/div>
Simulation Standard<\/div><\/div>

SmartSpice Tips: Memory Usage, .MODIF & .ALTER, Non-convergence<\/a><\/h3>
When you run a long simulation time analysis the evaluated time points are normally all held in memory until the end time\u2026<\/div><\/div><\/article>
March 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Guardian-Net Netlist Extractor: An Example of Specific Device Extraction Using XI-Scripts<\/a><\/h3>
Guardian LVS from Silvaco is an efficient, reliable, and diverse package that brings the benefit of high-speed verification to PC-based test environments.\u2026<\/div><\/div><\/article>
March 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Complex Parallel-Series Reduction<\/a><\/h3>
Silvaco\u2019s Guardian LVS tool compares two circuits that are defined by their netlists. The comparison is based strictly on the topological structure\u2026<\/div><\/div><\/article>
March 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Expert Editor Settings and Layer Cleaning<\/a><\/h3>
I generated some layers in Expert by DRC script run, and after that, derived layers can not be cleaned by "Tools\\Derived Layers\\Clean\u2026<\/div><\/div><\/article>
February 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Two-Dimensional ATLAS Device Simulation of Pentacene Organic Thin-film Transistors<\/a><\/h3>
Recent years has seen rapid acceleration in the research and development of organic thin film transistors (OTFTs) as key components for active\u2026<\/div><\/div><\/article>
February 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Exact2: Interconnect Parasitic Capacitance Simulator<\/a><\/h3>
Exact2 from Silvaco is a sophisticated, physically-based simulation tool for calculating semiconductor interconnect capacitance values. Its purpose is to build a capacitance\u2026<\/div><\/div><\/article>
February 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Laser Simulation Encompassing Molar Fraction Variation via DevEdit<\/a><\/h3>
This article addresses the creation of semiconductor laser double heterostructures, and the subsequent simulation of laser output with DevEdit from Silvaco. A\u2026<\/div><\/div><\/article>
February 1, 2003<\/div>
Simulation Standard<\/div><\/div>

The Importance of Mesh Definition in Strained-Si Heterostructure Simulation<\/a><\/h3>
Computer simulation is used extensively to verify physical phenomena in semiconductor devices. Meshing plays an essential role in obtaining good simulation results.\u2026<\/div><\/div><\/article>
February 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Optical Lithography Models in ATHENA<\/a><\/h3>
ATHENA\u2019s Optolith module is designed to simulate the 3 basic lithography technologies; contact printing, proximity and projection lithography. The imaging calculations within\u2026<\/div><\/div><\/article>
January 1, 2003<\/div>
Simulation Standard<\/div><\/div>

A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits<\/a><\/h3>
This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical\u2026<\/div><\/div><\/article>
January 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Behavioral Modeling and Simulation in the Scholar Schematic Environment<\/a><\/h3>
This article focusses on the use of Silvaco International\u2019s schematic capture and editing tool Scholar combined with Verilog A. Verilog A is\u2026<\/div><\/div><\/article>
January 1, 2003<\/div>
Simulation Standard<\/div><\/div>

SmartView \u2013 Integration Aspects and Key Attributes<\/a><\/h3>
This simulation standard will discuss Silvaco International\u2019s post processing application SmartView and will highlight features that identifying it as an important tool\u2026<\/div><\/div><\/article>
January 1, 2003<\/div>
Simulation Standard<\/div><\/div>

Getting an Accurate FFT Spectral Plot in SmartSpice<\/a><\/h3>
The transient simulation uses an adaptive time-stepping algorithm depending on the change in the circuit waveforms (dV\/dT). This means the simulated waveform\u2026<\/div><\/div><\/article>
December 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Real-time DRC Verification by DRC Guard<\/a><\/h3>
DRC Guard Performs "real-time" DRC on Expert Layout Editor.\u00a0DRC Guard\u2019s real-time design rule check (DRC) verifies entered or modified objects after the\u2026<\/div><\/div><\/article>
December 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Actual Examples of Creating Parameterized Cells<\/a><\/h3>
Silvaco\u2019s Expert tool is an extremely powerful layout-editing tool that supports features related to parameterized cells. Parameterized cells, often called P-cells, increase\u2026<\/div><\/div><\/article>
December 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Connectivity Operations in Guardian DRC<\/a><\/h3>
The article "Connectivity options for DRC spacing check operations in Guardian" (Simulation Standard, vol. 11, no. 12) [1] describes layout netlist connectivity\u2026<\/div><\/div><\/article>
December 1, 2002<\/div>
Simulation Standard<\/div><\/div>

How does Snap-to-grid Works for Cell Instances<\/a><\/h3>
We have lots of cells that become off-grid when we do cut-and-paste from other cells. We tried to use the "Tools->Snap Selected\u2026<\/div><\/div><\/article>
November 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Simulation of Single-Event Effects in FinFETs Using the ATLAS Device Simulator<\/a><\/h3>
A great deal of recent industry attention has focused on the use of non-planar multi-gate device structures in future generation MOS devices\u2026<\/div><\/div><\/article>
November 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Simulation of a Double Ridge Edge Emitting InGaAsP\/InP MQW Laser<\/a><\/h3>
In order to investigate the influence of ridge separation on the transverse optical modes of a double ridge edge multiple quantum well\u2026<\/div><\/div><\/article>
November 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Quantum Modeling Part I: Poisson-Schrodinger Solver<\/a><\/h3>
The trend toward smaller MOSFET devices with thinner gate oxide and greater doping is resulting in the increased importance of quantum mechanical\u2026<\/div><\/div><\/article>
November 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Simulation of a High Gain InP\/InGaAs\/InP Double HBT with Varying Doping Profile within ATLAS<\/a><\/h3>
It is possible to now create new heterojunction and double heterojunction bipolar transistors [2] utilizing junction layers made of different heterojunction semiconductor\u2026<\/div><\/div><\/article>
November 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Order of Multiple Implants in a Process Affects Results<\/a><\/h3>
When an implant occurs there will be some level of damage to the crystal structure of the silicon. If this damage is\u2026<\/div><\/div><\/article>
October 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Temperature Effects in SmartSpice LEVEL=6 Ferroelectric Capacitance Model From Ramtron<\/a><\/h3>
Implementation of a new ferroelectric capacitance model from Ramtron International Corporation into SmartSpice was first described in the April 2002 issue of\u2026<\/div><\/div><\/article>
October 1, 2002<\/div>
Simulation Standard<\/div><\/div>

UFSOI V7.0 (UFPDB V2.0) Model Released in SmartSpice<\/a><\/h3>
Version 7.0 of the University of Florida Silicon-On-Insulator (UFSOI), released in 2002, is now available with Silvaco SmartSpice by setting LEVEL to\u2026<\/div><\/div><\/article>
October 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Managing SmartSpice \/ SmartView Simulation Output Raw Files<\/a><\/h3>
Silvaco SmartSpice simulation results are typically stored in RAM. Since transient simulations of large circuits often exceed 1GB, a large swap-space partition\u2026<\/div><\/div><\/article>
October 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Defining Voltage Controlled Oscillators in SmartSpice<\/a><\/h3>
One of the methods to define a Voltage Controlled Oscillator (VCO) in a SPICE simulation is to make use of a voltage-controlled\u2026<\/div><\/div><\/article>
October 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Geometry Binning for TFT models and SmartSpice Tips<\/a><\/h3>
Level=36 RPI poly-Si TFT and other original TFT models do not support automatic geometry binning. The enhanced model included with SmartSpice 1.9.7.C\u2026<\/div><\/div><\/article>
September 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Advanced Features in Expert Layout Editing Tool: Parameterized Cells<\/a><\/h3>
Silvaco Expert is an extremely powerful layout-editing tool that supports features related to parameterized cells. Parameterized cells, often called P-cells, increase designer\u2026<\/div><\/div><\/article>
September 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Expert Wiring Tool: Router at Hand<\/a><\/h3>
Modern complex circuit designs require automatic router functionality in circuit layout editors. In multi-layer hierarchical design, it is often necessary to build\u2026<\/div><\/div><\/article>
September 1, 2002<\/div>
Simulation Standard<\/div><\/div>

C++ Language Interface for Expert Layout Editor<\/a><\/h3>
The C++ interface for Silvaco\u2019s Expert layout tool, is now an exclusive customization language that expands the tool\u2019s handling of high-level customization,\u2026<\/div><\/div><\/article>
September 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Running a DRC Check on a Design with Round Curves<\/a><\/h3>
After I create my round curve and run a DRC check on my design, it comes up with hundreds of errors associated\u2026<\/div><\/div><\/article>
August 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Simulating Boron Diffusion in Silicon Germanium<\/a><\/h3>
The silicon germanium heterojunction bipolar transistor (SiGe HBT) is a promising technology for combining the operating speed of compound material devices with\u2026<\/div><\/div><\/article>
August 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Simulating 3D Ohmic Heating Effects in Metal<\/a><\/h3>
A new feature has been added to Silvaco's device simulator ATLAS, which allows the simulation of ohmic heating effects in metals using\u2026<\/div><\/div><\/article>
August 1, 2002<\/div>
Simulation Standard<\/div><\/div>

The Valdinoci Temperature Dependent Impact Ionization Model for Silicon<\/a><\/h3>
Impact ionization plays an important role in the design of many semiconductor devices. Since impact ionization is both temperature and electric field\u2026<\/div><\/div><\/article>
August 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Reproducing Basic Experiments in ATLAS to Study the Transient Decay of Carriers<\/a><\/h3>
ATLAS may be used to study these effects. A standard experiment for studying recombination in silicon is the transient decay of photoexcited\u2026<\/div><\/div><\/article>
July 1, 2002<\/div>
Simulation Standard<\/div><\/div>

BSIM3SOI Version 3.0 Model Released in SmartSpice<\/a><\/h3>
BSIM3SOI version 3.0 model was released on May 2002 by UC Berkeley. This model includes both Partially and Fully depleted models. This\u2026<\/div><\/div><\/article>
July 1, 2002<\/div>
Simulation Standard<\/div><\/div>

A New Surface-Potentials Based MOSFET Model: HiSIM<\/a><\/h3>
HiSIM is based on a charge-sheet model. IDS current is described using only one equation, and there-fore is continuous over the whole\u2026<\/div><\/div><\/article>
July 1, 2002<\/div>
Simulation Standard<\/div><\/div>

HiSIM Version 1.0 Model Released in UTMOST III<\/a><\/h3>
HiSIM is a MOSFET model for SPICE circuit simulation that has been developed by Hiroshima University and STARC Company.\u00a0This model present several\u2026<\/div><\/div><\/article>
July 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Measure Low Current FT in Bipolar devices<\/a><\/h3>
The input impedence of most network analyzers are around 1 MOhm, which is relatively small. Due to this low impedence the leakage\u2026<\/div><\/div><\/article>
June 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Parallel DRC by Functional Decomposition of DRC Decks<\/a><\/h3>
A new version of Savage DRC system taps the full power of multiprocessor computers by introducing simultaneous execution of DRC commands from\u2026<\/div><\/div><\/article>
June 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Expert Layout Editor, Savage DRC System and Guardian LVS for Linux Platform<\/a><\/h3>
Silvaco Data Systems announces the release of CELEBRITY CAD suite: Expert layout editor, Savage DRC system and Guardian LVS for Linux platform.<\/div><\/div><\/article>
June 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Modification of BEM for Precise Capacitance Extraction<\/a><\/h3>
It is well-known that parasitic effects are no longer negligible for modern integrated circuit technology. Among the most important parasitic effects limiting\u2026<\/div><\/div><\/article>
June 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Advanced Layout Editing Using XI-scripts<\/a><\/h3>
To provide uniform etching of metal, dummy metal rectangles can be placed over an unused area of the chip. The following script\u2026<\/div><\/div><\/article>
June 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips, and Solutions for Expert Layout Editor<\/a><\/h3>
Q:\u00a0 How can I cut exactly the same hole in many layers? Q: How to skip a single layer during stream-out? Q:\u2026<\/div><\/div><\/article>
May 1, 2002<\/div>
Simulation Standard<\/div><\/div>

A Model for Boron T.E.D. in Silicon: Full Couplings of Dopant with Free and Clustered Interstitials<\/a><\/h3>
In this contribution we present a model for transient enhanced diffusion of boron in silicon. This model is based on the usual\u2026<\/div><\/div><\/article>
May 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Breakdown Analysis of a Body-Contacted Submicron High Electron Mobility Transistor<\/a><\/h3>
Interest continues to grow in the development of high electron mobility transistor (HEMT) technologies for micrometer and millimeter wave power applications. A\u2026<\/div><\/div><\/article>
May 1, 2002<\/div>
Simulation Standard<\/div><\/div>

QUEST: Frequency-Dependent RLCG Extractor Part 2 – Comparison with Experiments<\/a><\/h3>
This article presents a standard case of transmission line: the microstrip structure. First, the structure is described and then the results extracted\u2026<\/div><\/div><\/article>
May 1, 2002<\/div>
Simulation Standard<\/div><\/div>

ATLAS Simulation of a Schottky Contact<\/a><\/h3>
ATLAS allows the user to define a contact with a number of different boundary conditions; ohmic, Schottky, current controlled, floating or reflecting.\u00a0The\u2026<\/div><\/div><\/article>
April 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Verilog-A Release in SmartSpice<\/a><\/h3>
We give in this article an introduction to the Verilog-A SmartSpice interface. This new feature in SmartSpice allows the user to write\u2026<\/div><\/div><\/article>
April 1, 2002<\/div>
Simulation Standard<\/div><\/div>

New Ferroelectric Capacitance Model frmc from Ramtron Corporation in SmartSpice<\/a><\/h3>
Ramtron International Corporation has developed a ferroelectric capacitance model with a new concept of double distributions of domain reversal voltages.<\/div><\/div><\/article>
April 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Multiple Linear Solvers Introduced in SmartSpice<\/a><\/h3>
Acknowledging the need for more flexibility, SmartSpice now provides three numerical methods for linear system solution. The additional solvers provide for greater\u2026<\/div><\/div><\/article>
April 1, 2002<\/div>
Simulation Standard<\/div><\/div>

BSIM4 RF CMOS Modeling with UTMOST III<\/a><\/h3>
The BSIM4 model provides a RF CMOS modeling capability. Prior to the BSIM4 model the RF modeling was accomplished by using macro\u2026<\/div><\/div><\/article>
March 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Enhanced LVS Reports in Guardian and Their Inspection<\/a><\/h3>
It is well known that analyzing LVS reports is often a difficult and brain-teasing task because the "global" nature of connectivity. Unlike\u2026<\/div><\/div><\/article>
March 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Antenna Rule Checks in Savage<\/a><\/h3>
Antenna rules is a common name for rules that check ratios of amounts of material in two layers from the same node.\u2026<\/div><\/div><\/article>
March 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Expert’s Application Programming Interface (Expert API)<\/a><\/h3>
Expert API is intended for customizing and extending the existing software functionality by functions written by the users of Expert using C\/C++.<\/div><\/div><\/article>
March 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Add Custom Commands to Expert’s Menu<\/a><\/h3>
A simple way to add custom commands to Expert's menu is implemented. It is possible to add menu items that execute xi-commands\u2026<\/div><\/div><\/article>
February 20, 2002<\/div>
Simulation Standard<\/div><\/div>

Non-Stationary Transport Effects: Impact on Performances of Realistic 50nm MOSFET Technology<\/a><\/h3>
We analyze quantitatively the real impact of technology on the needed level for carrier transport modeling. The results, based on theoretical analyses,\u2026<\/div><\/div><\/article>
February 1, 2002<\/div>
Simulation Standard<\/div><\/div>

QUEST: Frequency-Dependent RLCG Extractor<\/a><\/h3>
Signals propagated in actual and future IC's interconnections are spreading, in terms of spectrum frequency, from DC to microwave domain because of\u2026<\/div><\/div><\/article>
February 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Modeling of Charge Distribution Using Schrodinger-Poisson Equations: Application to Double-Gate GAA-SOI Transistor<\/a><\/h3>
The Gate-All-Around SOI transistor [1], in which the gate oxide and the gate electrode are wrapped around the semiconductor region between the\u2026<\/div><\/div><\/article>
February 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Installing and using Silvaco TCAD tools on a Windows 2000 Machine<\/a><\/h3>
Installing and using Silvaco TCAD tools on a Windows 2000 Machine Introduction Silvaco software supports licensing on Windows NT (Serverice Pack 4.\u2026<\/div><\/div><\/article>
January 1, 2002<\/div>
Simulation Standard<\/div><\/div>

Modella PNP Bipolar Model Released in SmartSpice<\/a><\/h3>
The Modella lateral PNP bipolar model was\u00a0 developed by Philips Electronics N.V. and first released to the public domain in 1990 [1,2].\u2026<\/div><\/div><\/article>
January 1, 2002<\/div>
Simulation Standard<\/div><\/div>

New Berkeley BSIM4v2.1 MOSFET Model Available Within SmartSpice\/UTMOST III<\/a><\/h3>
So far the BSIM3v3.2 MOSFET model, developed by UC-Berkeley, has been considered as the industry standard model for deep-submicron CMOS design. It\u2026<\/div><\/div><\/article>
January 1, 2002<\/div>
Simulation Standard<\/div><\/div>

How to Achieve Good Parameter Optimization Using The New Methodology in UTMOST III Optimizer<\/a><\/h3>
Optimization is the task of finding the absolute best set of admissible conditions to achieve your objective, formulated in mathematical terms. The\u2026<\/div><\/div><\/article>
January 1, 2002<\/div>
Simulation Standard<\/div><\/div>

How to extract BSIM4 parameters using UTMOST III<\/a><\/h3>
The BSIM4_FI routine in UTMOST III MOS module should be used for data collection and BSIM4 SPICE model parameter extraction. The BSIM4_FI\u2026<\/div><\/div><\/article>
December 1, 2000<\/div>
Simulation Standard<\/div><\/div>

Connectivity Options for DRC Spacing Check Operations in Savage<\/a><\/h3>
An IC layout has to satisfy many technological design requirements. One of these is spacing, i.e., a layout object has to be\u2026<\/div><\/div><\/article>
December 1, 2000<\/div>
Simulation Standard<\/div><\/div>

Recent improvements in Expert, Savage, Guardian and Maverick<\/a><\/h3>
Most of recent improvements in Expert, Savage, Guardian and Maverick are aimed at the enhancement of the usability of these tools. All\u2026<\/div><\/div><\/article>
December 1, 2000<\/div>
Simulation Standard<\/div><\/div>

Optimal Packing of Orthoblocks For ULSI Floorplanning<\/a><\/h3>
Virtually all latest and prospective enhancements of Expert Layout processor (for example, semi-automatic floorplanning) are based on sophisticated geometrical models. In some\u2026<\/div><\/div><\/article>
December 1, 2000<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips and Solutions for Expert Layout Editor<\/a><\/h3>
If I try to close a project, Expert gives me a prompt: "Save changes in a project?", but I remember that I\u2026<\/div><\/div><\/article>
November 1, 2000<\/div>
Simulation Standard<\/div><\/div>

Simulating Impurity Freeze-Out During Low Temperature Operation<\/a><\/h3>
The low temperature operation of many device structures has been shown as an effective method for improving device performance without reducing device\u2026<\/div><\/div><\/article>
November 1, 2000<\/div>
Simulation Standard<\/div><\/div>

Simulation of Vertical Double-Gate SOI MOSFETs Using Device3D<\/a><\/h3>
This article will present the simulation methodology of a self-aligned double-gate MOSFET structure (FinFET) using SILVACO 3-D simulation suite. The double-gate MOSFET\u2026<\/div><\/div><\/article>
November 1, 2000<\/div>
Simulation Standard<\/div><\/div>

Non-Stationary Transport Effects: Impact on Performances of Realistic 50nm MOSFET Technology<\/a><\/h3>
We analyze quantitatively the real impact of technology on the needed level for carrier transport modeling. The results, based on theoretical analyzes,\u2026<\/div><\/div><\/article>
November 1, 2000<\/div>
Simulation Standard<\/div><\/div>

ATLAS can be used to perform large signal sinusoidal analysis<\/a><\/h3>
The Atlas syntax is flexible enough to allow the definition of sinusoidal nodal voltages by defining them on the SOLVE statement line.\u2026<\/div><\/div><\/article>
October 1, 2000<\/div>
Simulation Standard<\/div><\/div>

RF CMOS Modeling Using UTMOST III AC (S-Parameter) Module<\/a><\/h3>
This article presents a high frequency SPICE model parameter extraction method for CMOS devices. Current compact MOS models are developed for low\u2026<\/div><\/div><\/article>
October 1, 2000<\/div>
Simulation Standard<\/div><\/div>

New Improvements in TFT Models: Amorphous (Level=35) and Poly-Silicon (Level=36) TFT<\/a><\/h3>
New improvements have been added to Shur a-Si:H and Poly-Si Thin Film Transistors models. These enhancements include self-heating effect and a new\u2026<\/div><\/div><\/article>
October 1, 2000<\/div>
Simulation Standard<\/div><\/div>

BSIM4_U ( BSIM4 Universal Routine )<\/a><\/h3>
This routine is a multitarget\/geometry routine used to extract all kind of characteristics. There is the possibility to trace three different targets.\u2026<\/div><\/div><\/article>
October 1, 2000<\/div>
Simulation Standard<\/div><\/div>

Measure CJSWG (CJGATE) Capacitance using UTMOST III<\/a><\/h3>
For the UTMOST III versions greater than 17.2.0.R, the UTMOST users can measure the CJSWG (CJGATE) capacitance using the "CJ\/CJSW" routine. The\u2026<\/div><\/div><\/article>
September 1, 2000<\/div>
Simulation Standard<\/div><\/div>

Cross-Sectional Viewer in Expert<\/a><\/h3>
Cross-Sectional Viewer\u00a0is a tool within\u00a0Expert\u00a0to simulate the cross sectional view of ICs along an arbitrary drawn cut-line on the layout.\u00a0Cross-sectional Viewer\u00a0is a\u2026<\/div><\/div><\/article>
September 1, 2000<\/div>
Simulation Standard<\/div><\/div>

Expert: Recent Improvements in Hierarchical Layout Inspection<\/a><\/h3>
The functionality of several features of\u00a0Expert layout editor has been enhanced to deal with hierarchical layouts in more convenient ways.<\/div><\/div><\/article>
September 1, 2000<\/div>
Simulation Standard<\/div><\/div>

Applicability of Distance Computation for Graphs to LVS Discrepancy Analysis<\/a><\/h3>
An important step in electronic circuit design is layout versus schematic verification (LVS)<\/div><\/div><\/article>
September 1, 2000<\/div>
Simulation Standard<\/div><\/div>

Expert Hints, Tips, and Solutions: Object Scripting, Layer Color Palette, Big Measurements<\/a><\/h3>
Q: Often I need to measure big objects. It order to position the ruler precisely I must zoom in at one end,\u2026<\/div><\/div><\/article>
August 1, 2000<\/div>
Simulation Standard<\/div><\/div>

Yield Analysis and Performance Optimization Using FastBlaze and SPAYN<\/a><\/h3>
In previous Simulation Standard articles (Nov 97 & Nov 98) FastBlaze has been presented as a new, highly efficient approach to simulating\u2026<\/div><\/div><\/article>
August 1, 2000<\/div>
Simulation Standard<\/div><\/div>

New Model for Simulation of Exposure Process in Complex Nonplanar Resist-Substrate Structures<\/a><\/h3>
Predictive and efficient lithography simulation is an important component of the semiconductor industry efforts to develop the next generation of deep submicron\u2026<\/div><\/div><\/article>
August 1, 2000<\/div>
Simulation Standard<\/div><\/div>

Fast, Physical, Predictive and Calibrated Modeling of Ion Implantation<\/a><\/h3>
In a Research & Development environment, Technology Computer Aided Design (TCAD) is involved in the device optimization loop and requires efficient and\u2026<\/div><\/div><\/article>
August 1, 2000<\/div>
Simulation Standard<\/div><\/div>

Can Atlas be used to simulate advanced III-V or II-VI materials?<\/a><\/h3>
\u00a0Yes.\u00a0ATLAS\u00a0now supports a wide range of materials in its database. This database covers single element conductors, binary compounds and quaternary compounds. A\u2026<\/div><\/div><\/article>
July 1, 2000<\/div>
Simulation Standard<\/div><\/div>

Modeling and Parameter Extraction Technique for HV MOS Devices with BSIM3v3<\/a><\/h3>
In this paper, I have used the same technique to model uni-directional HV MOS devices as previously reported for bi-directional HV MOS\u2026<\/div><\/div><\/article>
July 1, 2000<\/div>
Simulation Standard<\/div><\/div>

New RF MOSFET Small Signal SPICE Model – Part 2<\/a><\/h3>
RF MOSFET Small - Signal Model and Parameters Small-signal equivalent circuit of MOSFET after de-embedding parasitics is shown in Figure 1 and\u2026<\/div><\/div><\/article>
July 1, 2000<\/div>
Simulation Standard<\/div><\/div>

UFSOI: Process-Based Compact SOI MOSFET Models<\/a><\/h3>
SOI technology appears now to have become an advantageous, viable option for low-voltage and high-performance CMOS integrated circuits in digital, analog, and\u2026<\/div><\/div><\/article>
June 5, 2000<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips, and Solutions June 2000<\/a><\/h3>
Q:\u00a0To simplify netlist extraction, I specify one kind of diffusion resistors in my layout by means of a special resistor definition layer.\u2026<\/div><\/div><\/article>
June 4, 2000<\/div>
Simulation Standard<\/div><\/div>

Parametric-Cells Implementation in Expert<\/a><\/h3>
A parameterized cell (P-Cell) is a cell with user-specified parameters. It is possible to create customized p-cell instances with different composition according\u2026<\/div><\/div><\/article>
June 3, 2000<\/div>
Simulation Standard<\/div><\/div>

Dragon DRC: Performance Improvement Techniques<\/a><\/h3>
Dragon\u00a0DRC is a new advanced hierarchical DRC system. The design principles this system is based on are carefully selected to ensure that\u00a0Dragon\u00a0DRC\u2026<\/div><\/div><\/article>
June 2, 2000<\/div>
Simulation Standard<\/div><\/div>

Maverick and Guardian – Enhancements<\/a><\/h3>
The latest release of Layout versus Schematic tools from\u00a0CELEBRITY CAD\u00a0suite (Maverick\u00a0full-chip parametric netlist extractor and\u00a0Guardian\u00a0hierarchical netlist comparator) delivers a number of significant\u2026<\/div><\/div><\/article>
June 1, 2000<\/div>
Simulation Standard<\/div><\/div>

Design Version Control System for Expert<\/a><\/h3>
The DVCS subsystem of\u00a0CELEBRITY CAD\u00a0suite provides significant improvement in management of complex designs, design reuse and teamwork management. The most important features\u2026<\/div><\/div><\/article>
May 4, 2000<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips, and Solutions February 2000<\/a><\/h3>
Q.\u00a0When I simulate my process flow the simulated profile is always lower than the SRP measurements. What could be causing this? A.\u2026<\/div><\/div><\/article>
May 3, 2000<\/div>
Simulation Standard<\/div><\/div>

Using Luminous to Model the Transient Response of a Silicon Charge Collection and Transfer Structure<\/a><\/h3>
The rapid evolution of modern photonic devices in digital photographic and detection systems creates a need for physically-based simulation of charge collection\u2026<\/div><\/div><\/article>
May 2, 2000<\/div>
Simulation Standard<\/div><\/div>

Calibrated and Predictive Simulation of Doping Profiles: Low Energy As, B and BF2 Ion Implantation<\/a><\/h3>
This article will present an efficient and original methodology for global and predictive modeling of low energy Boron, BF2 and Arsenic ion\u2026<\/div><\/div><\/article>
May 1, 2000<\/div>
Simulation Standard<\/div><\/div>

QUEST – Extraction of Frequency Dependent R, L, C, and G Transmission Line Models<\/a><\/h3>
A primary use of\u00a0QUEST\u00a0is intended to be for extracting frequency dependent transmission line models for use in SPICE circuit simulations. The generation\u2026<\/div><\/div><\/article>
April 28, 2000<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips, and Solutions April 2000<\/a><\/h3>
Q.\u00a0How can I extract VBIC bipolar model parameters using\u00a0UTMOST III? A.\u00a0UTMOST III\u00a0Bipolar module can be utilized to extract and optimize the VBIC\u2026<\/div><\/div><\/article>
April 3, 2000<\/div>
Simulation Standard<\/div><\/div>

NEW RF MOSFET Small Signal SPICE Model<\/a><\/h3>
With the advent of ever increasing operation frequencies, Silvaco is introducing a new high frequency model for MOSFETs that will be implemented\u2026<\/div><\/div><\/article>
April 2, 2000<\/div>
Simulation Standard<\/div><\/div>

JFET\/MESFET TRIQUINT Models (Level=5 and level=7)<\/a><\/h3>
Until now,\u00a0SmartSpice\u00a0has supported the TriQuint model designated TOM using the Level=5 model parameter.\u00a0SmartSpice\u00a0now supports the TriQuint-2 MESFET model designated TOM-2. This model\u2026<\/div><\/div><\/article>
April 1, 2000<\/div>
Simulation Standard<\/div><\/div>

New Version 5.0 of UFSOI Model Released in SmartSpice<\/a><\/h3>
The University of Florida SOI Group first released version 5.0 of UFSOI model in August 1999 and then in November 1999. To\u2026<\/div><\/div><\/article>
March 3, 2000<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips, and Solutions March 2000<\/a><\/h3>
Q:\u00a0Usually, when I want to change the display of a drawing in the Drawing window, I select the Window pull-down menu in\u2026<\/div><\/div><\/article>
March 2, 2000<\/div>
Simulation Standard<\/div><\/div>

Scholar – SmartSpice Interface<\/a><\/h3>
One of the most useful features of the\u00a0Scholar\u00a0schematic capture is tight integration with the\u00a0SmartSpice\u00a0simulator. In effect,\u00a0Scholar\u00a0makes it possible to automatically generate\u00a0SmartSpice\u00a0netlist on\u2026<\/div><\/div><\/article>
March 1, 2000<\/div>
Simulation Standard<\/div><\/div>

Inter-Tool Communication Within CAD CELEBRITY<\/a><\/h3>
One of the main features of modern complex Computer-Aided Design Systems is the ability to support the communication between concurrently executing applications\u2026<\/div><\/div><\/article>
February 4, 2000<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips, and Solutions February 2000<\/a><\/h3>
Q.\u00a0How can I ensure that the vertical Y.MESH spacing in my process simulation is adequate for my particular implant condition? A.\u00a0A good\u2026<\/div><\/div><\/article>
February 3, 2000<\/div>
Simulation Standard<\/div><\/div>

Reverse Engineering An AlGaAs\/InGaAs PHEMT With FastBlaze<\/a><\/h3>
FastBlaze\u00a0is an ultra-fast physical MESFET and HEMT simulator which incorporates advanced physical models. By designing the simulator and its framework specifically for\u2026<\/div><\/div><\/article>
February 2, 2000<\/div>
Simulation Standard<\/div><\/div>

ATLAS Field Dependent Mobility: Model Parameters for (0001) 6H-SiC and (0001) 4H-SiC<\/a><\/h3>
For high temperature, high power applications Silicon Carbide (SiC) continues to be a useful material for device fabrication because of its wide\u2026<\/div><\/div><\/article>
February 1, 2000<\/div>
Simulation Standard<\/div><\/div>

Investigating Two Dimensional Implantation Effects Using The BCA Model<\/a><\/h3>
The Monte Carlo Binary Collision Algorithm (BCA) implant module in\u00a0ATHENA\u00a0was introduced in an earlier article [Simulation Standard Vol 10, #5, May 1999]\u2026<\/div><\/div><\/article>
January 3, 2000<\/div>
Simulation Standard<\/div><\/div>

Hints & Tips January 1999<\/a><\/h3>
A.\u00a0UTMOST III\u00a0SOI module has three routines for characterization of the parasitic BJTs of SOI devices. These routines are "IC\/VCE", "Gummel" and "INT_BJT"\u2026<\/div><\/div><\/article>
January 2, 2000<\/div>
Simulation Standard<\/div><\/div>

VBIC Version 1.2 Released in SmartSpice and UTMOST III<\/a><\/h3>
The latest VBIC bipolar model v1.2 of Sep 24 1999 has been integrated into\u00a0SmartSpice\u00a0and\u00a0UTMOST III.\u00a0It can be invoked by specifying the model\u2026<\/div><\/div><\/article>
January 1, 2000<\/div>
Simulation Standard<\/div><\/div>

RF CMOS Device Modeling: BSIM-Based Physical Model with Root-Like Construction Approach – Small Signal Modeling<\/a><\/h3>
A novel extraction method of high frequency small-signal model parameters for MOSFET is proposed. From S-parameter measurement, this technique accurately extracts the\u2026<\/div><\/div><\/article>
December 2, 1999<\/div>
Simulation Standard<\/div><\/div>

Hints & Tips December 1999<\/a><\/h3>
Q:\u00a0I tried to resize shapes using the DRC command and observed thin "cracks" appeared for polygons with holes (see the left shape\u2026<\/div><\/div><\/article>
December 1, 1999<\/div>
Simulation Standard<\/div><\/div>

An Intuitive Front-End to Effective and Efficient Schematic Capture Design<\/a><\/h3>
In our previous publication ("Scholar:\u00a0An Enhanced Multi-Platform Schematic Capture",\u00a0Simulation Standard, Vol.10, Number 9, September 1999) we presented the main features of a\u2026<\/div><\/div><\/article>
November 5, 1999<\/div>
Simulation Standard<\/div><\/div>

Hints & Tips November 1999<\/a><\/h3>
A:\u00a0ATLAS\/S-Pisces\u00a0and\u00a0ATLAS\/Blaze\u00a0both have a small signal ac analysis capability built into them. This analysis is based upon the work of S.Laux [1] and\u2026<\/div><\/div><\/article>
November 4, 1999<\/div>
Simulation Standard<\/div><\/div>

Modeling Bidirectional Thyristors Using ATLAS<\/a><\/h3>
Thyristors are semiconductor devices that exhibit multi-stable or bi-stable electrical characteristics, and can be switched between a high-impedance OFF state and a\u2026<\/div><\/div><\/article>
November 3, 1999<\/div>
Simulation Standard<\/div><\/div>

Modelling Tunneling Currents in Ultra Thin Oxides<\/a><\/h3>
Ever decreasing minimum geometries in MOSFET design results in a corresponding reduction in the thickness of the gate oxide. This is an\u2026<\/div><\/div><\/article>
November 2, 1999<\/div>
Simulation Standard<\/div><\/div>

Optoelectric Device Simulation of a Dual-Base BJT Using Luminous<\/a><\/h3>
With the continuing emergence of optical technologies, optoelectronic device structures are becoming increasingly important for modern telecommunications and data network applications. Like\u2026<\/div><\/div><\/article>
November 1, 1999<\/div>
Simulation Standard<\/div><\/div>

The Industry Standard of SOI Technology From Process To Circuit Simulation<\/a><\/h3>
SOI technology for state of the art CMOS technology is rapidly approaching maturity. PD-SOI device design has the advantage of easier manufacturing\u2026<\/div><\/div><\/article>
October 3, 1999<\/div>
Simulation Standard<\/div><\/div>

Hints & Tips October 1999<\/a><\/h3>
A.\u00a0It is likely that there may be some contact problems or defected devices during the data collection. This problem can occur when\u2026<\/div><\/div><\/article>
October 2, 1999<\/div>
Simulation Standard<\/div><\/div>

New Improvements in TFT Models: Amorphous (Level=35) and Poly-Silicon (Level=36) TFT<\/a><\/h3>
New improvements have been added to Shur models. These enhancements include a self-heating effect and a new charge conservative model.<\/div><\/div><\/article>
October 1, 1999<\/div>
Simulation Standard<\/div><\/div>

BSIM3SOI Version 2.1 (FD, DD and PD) Models Released in SmartSpice<\/a><\/h3>
The Berkeley BSIM3SOI version 2.1 models, released in September 1999, have been implemented in\u00a0SmartSpice. The three new models are selected according to\u2026<\/div><\/div><\/article>
September 2, 1999<\/div>
Simulation Standard<\/div><\/div>

Hints & Tips September 1999<\/a><\/h3>
Q: How can I cut exactly the same hole in many layers? A: There are at least two ways to do this.\u2026<\/div><\/div><\/article>
September 1, 1999<\/div>
Simulation Standard<\/div><\/div>

Scholar: An Enhanced Multi-Platform Schematic Capture<\/a><\/h3>
One of the main features of modern complex CAD systems consists in the ability to support the schematic capture function that provides\u2026<\/div><\/div><\/article>
August 4, 1999<\/div>
Simulation Standard<\/div><\/div>

Hints & Tips August 1999<\/a><\/h3>
A:\u00a0Modeling of the increase in breakdown voltage at elevated temperatures requires a model to describe the temperature dependence of the impact ionization\u2026<\/div><\/div><\/article>
August 3, 1999<\/div>
Simulation Standard<\/div><\/div>

High Performance ATHENA and ATLAS Simulation on PC under NT<\/a><\/h3>
The recent advances in PC hardware capability in terms of memory and CPU floating point performance has allowed the possibility of running\u2026<\/div><\/div><\/article>
August 2, 1999<\/div>
Simulation Standard<\/div><\/div>

New Thermionic Emission and Tunneling Models in ATLAS<\/a><\/h3>
In order to simulate heterojunction devices accurately, both the thermionic emission and tunneling mechanisms must be considered when calculating transport across hetrojunctions.\u2026<\/div><\/div><\/article>
August 1, 1999<\/div>
Simulation Standard<\/div><\/div>

Generating a Capacitance Coefficient Database for any Chip Level LPE Tool Using EXACT<\/a><\/h3>
EXACT\u00a0is a sophisticated interconnect characterization tool integrated into the\u00a0DISCOVERY\u00a0framework. It is designed to build the capacitance coefficient database required by any Layout\u2026<\/div><\/div><\/article>
July 3, 1999<\/div>
Simulation Standard<\/div><\/div>

Hints & Tips July 1999<\/a><\/h3>
The "Binning" routine in\u00a0UTMOST III\u00a0MOS module has been greatly enhanced. The bin models can be generated much faster and the routine requires\u2026<\/div><\/div><\/article>
July 2, 1999<\/div>
Simulation Standard<\/div><\/div>

MOS31 JFET\/MOSFET Model Now Available in SmartSpice<\/a><\/h3>
Silvaco now offers the MOS31 JFET\/MOSFET model originally developed by Philips [1] as part of the\u00a0SmartLib\u00a0product-independent model library. This model is available\u2026<\/div><\/div><\/article>
July 1, 1999<\/div>
Simulation Standard<\/div><\/div>

New SOI UTMOST Module<\/a><\/h3>
Bulk CMOS is currently the dominant technology for VLSI integrated circuits but its scaling constraints pose ever greater as device geometries shrink.\u2026<\/div><\/div><\/article>
June 4, 1999<\/div>
Simulation Standard<\/div><\/div>

Hints & Tips May 1999<\/a><\/h3>
A. Previous articles in the Simulation Standard have highlighted the diffusion models required for accurate simulation of shallow source\/drain junction formation[1] and\u2026<\/div><\/div><\/article>
June 2, 1999<\/div>
Simulation Standard<\/div><\/div>

Hints & Tips June 1999<\/a><\/h3>
Q:\u00a0I want to draw several long wires, with precise positioning of both ends. I am used to doing this as follows:<\/div><\/div><\/article>
June 1, 1999<\/div>
Simulation Standard<\/div><\/div>

Maverick- Hierarchcal Full-Chip Extractor Recent Significant Advances<\/a><\/h3>
Maverick\u00a0is a sophisticated full chip hierarchical netlist extractor [1]. It augments the existing\u00a0CELEBRITY\u00a0framework which includes state-of-the-art software for VLSI layout editing, hierarchical\u2026<\/div><\/div><\/article>
May 3, 1999<\/div>
Simulation Standard<\/div><\/div>

Circuit Performance Analysis of Multiple ATHENA Transistors Using MixedMode<\/a><\/h3>
In a previous issue of Simulation Standard for Process and Device Engineers[1] the simulation of a three stage CMOS ring oscillator using\u00a0ATLAS\/MixedMode\u00a0was\u2026<\/div><\/div><\/article>
May 2, 1999<\/div>
Simulation Standard<\/div><\/div>

Continous Trap Model for Accurate Device Simulation of Polysilicon TFTs<\/a><\/h3>
There has been a significant increase in the popularity of liquid crystal displays with control circuitry being placed on to the glass\u2026<\/div><\/div><\/article>
May 1, 1999<\/div>
Simulation Standard<\/div><\/div>

Very Low Energy Boron Implant Simulation Using New BCA Monte-Carlo Model<\/a><\/h3>
ATHENA\u00a0version 5.0 includes a new Binary Collision Algorithm (BCA) for accurate Monte-Carlo implant modeling down to sub-1keV energies. This new BCA code\u2026<\/div><\/div><\/article>
April 3, 1999<\/div>
Simulation Standard<\/div><\/div>

Hints & Tips April 1999<\/a><\/h3>
A.\u00a0The BSIM3_MG routine in SOI module of\u00a0UTMOST III\u00a0can be used to extract SOI model parameters. The SOI BSIM3_MG routine operation is similar\u2026<\/div><\/div><\/article>
April 3, 1999<\/div>
Simulation Standard<\/div><\/div>

SPAYN: Golden Device Search Algorithm, EKV MOSFET Model and Improved GUI<\/a><\/h3>
The addition of important features in the latest version of\u00a0SPAYN\u00a0(1.7.3.R) makes it an even more useful and versatile statistical parameter and yield\u2026<\/div><\/div><\/article>
April 2, 1999<\/div>
Simulation Standard<\/div><\/div>

Mixed-Signal Simulation with SmartSpice in the Cadence Design Framework II<\/a><\/h3>
Users of the Cadence Design Framework II (DFII, versions 4.4.0 and above) have been enjoying a tight integration between\u00a0SmartSpice\u00a0and the Analog Artist\u2026<\/div><\/div><\/article>
April 1, 1999<\/div>
Simulation Standard<\/div><\/div>

Intrinsic Capacitance Parameter Extraction in UTMOST III<\/a><\/h3>
The intrinsic capacitance parameter extraction routine (INTCAP) is in the CAP analysis section of the\u00a0UTMOST III\u00a0MOS module (Routine#67). The INTCAP routine has\u2026<\/div><\/div><\/article>
March 3, 1999<\/div>
Simulation Standard<\/div><\/div>

Hints & Tips March 1999<\/a><\/h3>
Q:\u00a0I often use the temporary reference point, but I would like to see both absolute coordinates and relative coordinates, without toggling the\u2026<\/div><\/div><\/article>
March 2, 1999<\/div>
Simulation Standard<\/div><\/div>

Advanced Pairwise Merging Algorithm for VLSI Floorplanning<\/a><\/h3>
This paper concerns the problem of determining optimal placement of rectangular blocks within a rectangular area known as the packing or cutting-stock\u2026<\/div><\/div><\/article>
March 1, 1999<\/div>
Simulation Standard<\/div><\/div>

Introducing Guardian – LVS Verification for PC-based Platforms<\/a><\/h3>
Guardian\u00a0is a (state-of-the-art) hierarchical netlist comparison system, which eliminates many of the disadvantages of existing programs. Running on PCs under Windows NT,\u2026<\/div><\/div><\/article>
February 2, 1999<\/div>
Simulation Standard<\/div><\/div>

Mixed Circuit Device Simulation of Single Event Upset in a Memory Cell<\/a><\/h3>
This article presents Single Event Upset (SEU) simulation of a SRAM cell using\u00a0MixedMode3D. MixedMode3D\u00a0provides the capability to simultaneously perform circuit simulation coupled\u2026<\/div><\/div><\/article>
February 1, 1999<\/div>
Simulation Standard<\/div><\/div>

New, Fast Numerical Algorithm for Diffusion Modeling Implemented in ATHENA Version 5.0<\/a><\/h3>
A new diffusion algorithm based on a Galerkin method with linear finite elements, an extremely fast sparse matrix solver, and object oriented\u2026<\/div><\/div><\/article>
January 5, 1999<\/div>
Simulation Standard<\/div><\/div>

Hints & Tips January 1999<\/a><\/h3>
A.\u00a0Typically,\u00a0UTMOST III\u00a0s-parameter module is used to measure the FT versus IC (collector current) characteristic of bipolar transistors. The FT_CE routine can also\u2026<\/div><\/div><\/article>
January 4, 1999<\/div>
Simulation Standard<\/div><\/div>

New Parameters for TFT model: Amorphous (Level=35) and Poly-Silicon (Level=36) TFT<\/a><\/h3>
Several enhancements have been made to the TFT models in\u00a0SmartSpice.\u00a0New parameters have been added to improve accuracy and allow simular sophisticated modeling\u2026<\/div><\/div><\/article>
January 3, 1999<\/div>
Simulation Standard<\/div><\/div>

Enhanced Statistical Features in SPAYN Version 1.7.2<\/a><\/h3>
When performing statistical analyses it is often necessary to compute transformations of the observed data. This transformation may only involve a single\u2026<\/div><\/div><\/article>
January 2, 1999<\/div>
Simulation Standard<\/div><\/div>

New Built-in Dichotomic Search Algorithm in Smartspice<\/a><\/h3>
General purpose dichotomic search method is often requested by designers when they want to find a specific element (voltage, current, parameter value\u2026<\/div><\/div><\/article>
January 1, 1999<\/div>
Simulation Standard<\/div><\/div>

PHILIPS Model 9 New MM9 Extraction Routine in UTMOST III<\/a><\/h3>
Philips Level 9 model is widely used as an accurate deep submicron CMOS model. The model is physical, and as such lands\u2026<\/div><\/div><\/article>
December 3, 1998<\/div>
Simulation Standard<\/div><\/div>

HINTS & TIPS – December 1998<\/a><\/h3>
Q: I took the example file mux4.gds from Expert's installation and tried the Edit-in-place operation. I entered into an instance of mux1,\u2026<\/div><\/div><\/article>
December 2, 1998<\/div>
Simulation Standard<\/div><\/div>

LISA Powerful Script language for Expert<\/a><\/h3>
This article introduces the\u00a0LISA\u00a0(Language for Interfacing Silvaco Applications) command language and gives an overview of\u00a0LISA\u00a0features.<\/div><\/div><\/article>
December 1, 1998<\/div>
Simulation Standard<\/div><\/div>

Expert Expanded with Client-Server Project\/Library Management<\/a><\/h3>
The\u00a0Expert\u00a0layout processor v.2.0 introduces a client-server system for managing large projects in multiuser design environments. This system is a significant improvement and\u2026<\/div><\/div><\/article>
November 5, 1998<\/div>
Simulation Standard<\/div><\/div>

HINTS & TIPS – November 1998<\/a><\/h3>
Q:\u00a0How can anti-reflective coatings be modeled when simulating photodetectors in ATLAS\/Luminous? How can detection efficiency be plotted?A:\u00a0Earlier version of\u00a0ATLAS\u00a0were able to handle\u2026<\/div><\/div><\/article>
November 4, 1998<\/div>
Simulation Standard<\/div><\/div>

New Model for High Energy Implants in ATHENA<\/a><\/h3>
In our earlier paper [1] a new Binary Collision Approximation (BCA) module was described. It was shown that models and algorithms implemented\u2026<\/div><\/div><\/article>
November 3, 1998<\/div>
Simulation Standard<\/div><\/div>

Calibrating a Typical Bipolar Process Flow<\/a><\/h3>
A common request from TCAD (Technology Computer Aided Design) users is advise on how to calibrate the process flow and device simulator\u2026<\/div><\/div><\/article>
November 2, 1998<\/div>
Simulation Standard<\/div><\/div>

Accurate, High Speed Physics in FastBlaze<\/a><\/h3>
FastBlaze\u00a0uses novel device simulation techniques to simulate typical MESFET and HEMT characteristics in less than a minute. To be a truly useful\u2026<\/div><\/div><\/article>
November 1, 1998<\/div>
Simulation Standard<\/div><\/div>

Validation of CLEVER Interconnect Parasitics with 0.18 \u00b5m Process Measurements Benoit Froment and Herve Jaouen – SGS-Thomson Microelectronics<\/a><\/h3>
Parasitics+Netlist<\/span><\/div>
CLEVER\u00a0can perform accurate field solver extractions of resistance and capacitance from 3D structures generated from realistic process simulation. Comparison of\u00a0CLEVER\u00a0results with measurements\u2026<\/div><\/div><\/article>
October 5, 1998<\/div>
Simulation Standard<\/div><\/div>

HINTS & TIPS – October 1998<\/a><\/h3>
The HP4155\/56 DC Analyzer can be configured with SMU and Pulse Generator expander box frame called HP41501A. The expander box can have\u2026<\/div><\/div><\/article>
October 4, 1998<\/div>
Simulation Standard<\/div><\/div>

SPAYN Recent Developments<\/a><\/h3>
An important aspect of statistical process control in IC production is the ability to predict circuit performance variation in the manufacturing process.\u2026<\/div><\/div><\/article>
October 3, 1998<\/div>
Simulation Standard<\/div><\/div>

Scholar<\/a><\/h3>
The debut of Silvaco's new schematic editor,\u00a0Scholar, is drawing closer.\u00a0Scholar\u00a0is a sophisticated design tool which derives its power and flexibility from the\u2026<\/div><\/div><\/article>
October 2, 1998<\/div>
Simulation Standard<\/div><\/div>

PHILIPS Model 9<\/a><\/h3>
In collaboration with STMicroelectronics Central R&D at Crolles (France), a new routine has been developed in\u00a0UTMOST III\u00a0to provide a complete solution for\u2026<\/div><\/div><\/article>
October 1, 1998<\/div>
Simulation Standard<\/div><\/div>

Parallel .ALTER Statements in SmartSpice<\/a><\/h3>
The\u00a0.ALTER\u00a0statement is designed to allow a SPICE input deck to be re-run with a change in a single parameter. This feature is\u2026<\/div><\/div><\/article>
September 3, 1998<\/div>
Simulation Standard<\/div><\/div>

HINTS & TIPS – September 1998<\/a><\/h3>
I run DRC, find one-two violations, correct them, then I re-run DRC to check whether my corrections worked. However re-running on the\u2026<\/div><\/div><\/article>
September 2, 1998<\/div>
Simulation Standard<\/div><\/div>

Recursive Cutting of Rectangular Partitions for VLSI Floorplanning<\/a><\/h3>
Rectangular partitionings form a mathematical base for many modern approaches to automation of VLSI design [1-3]. In particular, popular methodologies of hierarchical\u2026<\/div><\/div><\/article>
September 1, 1998<\/div>
Simulation Standard<\/div><\/div>

Real-time DRC in Expert Layout Editor<\/a><\/h3>
In this paper we introduce one of the latest and most advanced features of Silvaco's\u00a0Expert\u00a0Layout processor for Windows NT \u00ad DRC Guard.\u2026<\/div><\/div><\/article>
August 4, 1998<\/div>
Simulation Standard<\/div><\/div>

HINTS & TIPS – August 1998<\/a><\/h3>
When using the analytical implant tables in\u00a0ATHENA\u00a0the default model for the lateral implant range assumes a gaussian profile with a standard deviation\u2026<\/div><\/div><\/article>
August 3, 1998<\/div>
Simulation Standard<\/div><\/div>

Simulating Redeposition During Etch Using a Monte Carlo Plasma Etch Model<\/a><\/h3>
The shrinking critical dimensions of modern technology place a heavy requirement on optimizing the etching of narrow mask opening. In addition the\u2026<\/div><\/div><\/article>
August 2, 1998<\/div>
Simulation Standard<\/div><\/div>

Fourier Transform Analysis for Large Signal Frequency Response in ATLAS<\/a><\/h3>
The\u00a0ATLAS\u00a0device simulation framework has been to improve the analysis the large signal transient behavior. These features include a simple specification for single\u2026<\/div><\/div><\/article>
August 1, 1998<\/div>
Simulation Standard<\/div><\/div>

Simulating Accurate 3D Geometries for Interconnect Parasitic Extraction Using CLEVER<\/a><\/h3>
CLEVER\u00a0is designed to model interconnect parasitics by simulating the back end processing steps of custom cells in three dimensions. A 3D process\u2026<\/div><\/div><\/article>
July 5, 1998<\/div>
Simulation Standard<\/div><\/div>

HINTS & TIPS – July 1998<\/a><\/h3>
The traditional Noise models in SPICE used two parameters (AF and KF) to model the noise level and the frequency dependency of\u2026<\/div><\/div><\/article>
July 4, 1998<\/div>
Simulation Standard<\/div><\/div>

UTMOST File Format Extension<\/a><\/h3>
Following the log file conversion tool for\u00a0TonyPlot\u00a0introduced with\u00a0UTMOST\u00a012.3.14.R1, new file formats have been added to\u00a0UTMOST III's printing and plotting options to make\u2026<\/div><\/div><\/article>
July 3, 1998<\/div>
Simulation Standard<\/div><\/div>

SmartSpice v.1.5.5 Release Notes<\/a><\/h3>
The latest Berkeley BSIM3v3.2 model of June 16 1998 has been integrated into\u00a0SmartSpice 1.5.5.\u00a0The Silvaco implementation of the Berkeley BSIM3v3.2 model can\u2026<\/div><\/div><\/article>
July 2, 1998<\/div>
Simulation Standard<\/div><\/div>

EKV MOSFET Model Version 2.6 Now Available in SmartSpice and UTMOST III<\/a><\/h3>
Silvaco now offers the EKV (ENZ, KRUMMENACHER, VITTOZ) MOSFET model version 2.6 originally developed in EPFL ("Ecole Polytechnique Federale de Lausanne" -\u2026<\/div><\/div><\/article>
July 1, 1998<\/div>
Simulation Standard<\/div><\/div>

BSIM3v3.2 Model Released in SmartSpice and UTMOST III<\/a><\/h3>
The latest Berkeley BSIM3v3.2 model of June 16 1998 is now available in the SmartSpice 1.5.5 release. Two BSIM3v3.2 implementations are supported\u2026<\/div><\/div><\/article>
June 3, 1998<\/div>
Simulation Standard<\/div><\/div>

HINTS AND TIPS – June 1998<\/a><\/h3>
Q:\u00a0Can I draw tangents to circles in EXPERT? A:\u00a0Expert supports several options for drawing sophisticated shapes. There are three ways to accomplish\u2026<\/div><\/div><\/article>
June 2, 1998<\/div>
Simulation Standard<\/div><\/div>

Optimum Standard Cell Layout Using Weighted Cycle Linear Placement<\/a><\/h3>
Placement and routing problems for integrated circuits are inherently interrelated and extremely complex from the algorithmic point of view. This complexity grows\u2026<\/div><\/div><\/article>
June 1, 1998<\/div>
Simulation Standard<\/div><\/div>

Maverick: Hierarchical Netlist Extractor for PC Platforms<\/a><\/h3>
Maverick is a modern hierarchical netlist extractor, providing extraordinary efficiency as well as comprehensive features and ease of use. It runs on\u2026<\/div><\/div><\/article>
May 5, 1998<\/div>
Simulation Standard<\/div><\/div>

HINTS AND TIPS – May 1998<\/a><\/h3>
How can anti-reflective coatings be modeled when simulating photodetectors in ATLAS\/Luminous? How can detection efficiency be plotted?<\/div><\/div><\/article>
May 4, 1998<\/div>
Simulation Standard<\/div><\/div>

Calibrating Reverse Short Channel Effects in MOSFETs<\/a><\/h3>
This article focuses on the effects of process and modeling parameters on device electrical characteristics and uses the threshold voltage versus gate\u2026<\/div><\/div><\/article>
May 4, 1998<\/div>
Simulation Standard<\/div><\/div>

Low-Power Systems-on-a-Chip CAD<\/a><\/h3>
Mixed-signal systems-on-a-chip (SOC) integration of digital, analog, RF, and power components is emerging to meet demands for low-power, highly integrated systems in\u2026<\/div><\/div><\/article>
May 1, 1998<\/div>
Simulation Standard<\/div><\/div>

Ultra-Fast Device Simulation with Monte Carlo Tuned Transport Models in FastBlaze<\/a><\/h3>
FastBlaze is a fast physical device simulator for MESFETs and HEMTs optimized to provide interactive TCAD for modern III-V FET devices. It\u2026<\/div><\/div><\/article>
April 7, 1998<\/div>
Simulation Standard<\/div><\/div>

HINTS & TIPS – April 1998<\/a><\/h3>
Q.\u00a0What is the typical method of measuring flicker noise using S3245A Noise Amplifier?<\/div><\/div><\/article>
April 6, 1998<\/div>
Simulation Standard<\/div><\/div>

SPICE Model Validation<\/a><\/h3>
The importance of the MOS device SPICE model validation and the introduction of the validation routine in UTMOST III was presented in\u2026<\/div><\/div><\/article>
April 5, 1998<\/div>
Simulation Standard<\/div><\/div>

UTMOST Log File Conversion for TonyPlot<\/a><\/h3>
A new feature has recently been added to\u00a0UTMOST: the ability to convert\u00a0UTMOST\u00a0log files into a format suitable for viewing in\u00a0TonyPlot. This new\u2026<\/div><\/div><\/article>
April 5, 1998<\/div>
Simulation Standard<\/div><\/div>

Advanced Cell Characterization Using SmartSpice Scripting Features<\/a><\/h3>
In a previous article [1], the efficient use of the\u00a0SmartSpice\u00a0.MODIF\u00a0statement for cell characterization was discussed. This article will focus on using advanced\u2026<\/div><\/div><\/article>
April 3, 1998<\/div>
Simulation Standard<\/div><\/div>

Release of RPI Amorphous Silicon and Polysilicon TFT Models in SmartSpice and UTMOST<\/a><\/h3>
Thin film transistors (TFTs) have an important application in the manufacture of active matrix LCD displays. As this technology has become more\u2026<\/div><\/div><\/article>
April 2, 1998<\/div>
Simulation Standard<\/div><\/div>

Release of an Upgraded SmartSpice Interface to Cadence<\/a><\/h3>
The\u00a0SmartSpice\u00a0Interface to Cadence integrates the Analog Artist and Composer elements of the Cadence Design Framework II (DFII) with\u00a0SmartSpice. This integration is accomplished,\u2026<\/div><\/div><\/article>
April 2, 1998<\/div>
Simulation Standard<\/div><\/div>

ATLAS\/MixedMode Simulation of a Three Stage CMOS Ring Oscillator Part I: MixedMode Setup<\/a><\/h3>
Ring oscillator circuits are a valuable test structure for determining the feasibility and success of an integrated circuit process fabrication sequence. One\u2026<\/div><\/div><\/article>
April 1, 1998<\/div>
Simulation Standard<\/div><\/div>

BSIM3SOI Level=25 Model Released in SmartSpice<\/a><\/h3>
The Berkeley BSIM3SOI model, released in December 1997, is now available within\u00a0SmartSpice\u00a0as the MOSFET level=25 model. This model incorporates three separate implementations:\u2026<\/div><\/div><\/article>
March 3, 1998<\/div>
Simulation Standard<\/div><\/div>

Scanbox Approach to Shape Reconstruction for Automated Reticle Inspection<\/a><\/h3>
The paper describes a generalization of the scanline approach [1] to reconstruction of the shape of planar object represented by a discrete\u2026<\/div><\/div><\/article>
March 3, 1998<\/div>
Simulation Standard<\/div><\/div>

Savage Enhanced with Recognition and Reporting of Hierarchical Structure of Errors<\/a><\/h3>
This article describes a method of reporting DRC errors implemented in\u00a0Savage, applicable to multi-million transistor layouts. The method of hierarchical information inheritance\u2026<\/div><\/div><\/article>
March 2, 1998<\/div>
Simulation Standard<\/div><\/div>

Circuit Verification via Hypergraph Realization<\/a><\/h3>
One of the most challenging and time consuming tasks in VLSI design automation is Layout Versus Schematic (LVS). The problem is to\u2026<\/div><\/div><\/article>
March 1, 1998<\/div>
Simulation Standard<\/div><\/div>

HINTS & TIPS – March 1998<\/a><\/h3>
Q:\u00a0Is it possible to perform a DRC check on portions rather than on the whole circuit useful when only 2 or 3\u2026<\/div><\/div><\/article>
February 5, 1998<\/div>
Simulation Standard<\/div><\/div>

3D Simulation of Power Devices Using Giga3D and MixedMode3D<\/a><\/h3>
Recent additions to the ATLAS device simulation framework have added the ability to simulate 3D electrothermal effects in Giga3D and mixed circuit\u2026<\/div><\/div><\/article>
February 4, 1998<\/div>
Simulation Standard<\/div><\/div>

MixedMode Simulation of Power Electronic Converters<\/a><\/h3>
With mounting concern for energy conservation and nature preservation, power electronics is becoming increasingly dominant in everyday life.<\/div><\/div><\/article>
February 3, 1998<\/div>
Simulation Standard<\/div><\/div>

Polysilicon Gate Depletion Effects in Sub-Micron MOSFETs<\/a><\/h3>
It is usually assumed that the poly gate in a MOSFET is doped at a concentration such that depletion in the gate\u2026<\/div><\/div><\/article>
February 2, 1998<\/div>
Simulation Standard<\/div><\/div>

Mesh Control in ATHENA Avoiding Problems and What to do If they Occur<\/a><\/h3>
Mesh control in process simulators is one of the major issues tackled by any user. Over the years the meshing algorithms with\u00a0SSuprem4\u00a0and\u00a0ATHENA\u00a0have\u2026<\/div><\/div><\/article>
February 1, 1998<\/div>
Simulation Standard<\/div><\/div>

HINTS & TIPS – February 1998<\/a><\/h3>
Q:\u00a0How can external tools be run inside of Silvaco's run-time environment DeckBuild? Is it possible to include UNIX commands along with simulator\u2026<\/div><\/div><\/article>
January 4, 1998<\/div>
Simulation Standard<\/div><\/div>

The SmartSpice Interface to Cadence (revisited)<\/a><\/h3>
The SmartSpice interface to the Cadence Design Framework II has been substantially improved in its latest release (version 1.0.8.R), following feedback from\u2026<\/div><\/div><\/article>
January 3, 1998<\/div>
Simulation Standard<\/div><\/div>

CellRATER from Taveren Technology fast, Accurate Cell Library Characterization for Deep Submicron Timing Flow Improvement<\/a><\/h3>
Taveren Technology, Inc., a startup company based in Austin, Texas is busy developing the next generation performance characterization tool suite.<\/div><\/div><\/article>
January 2, 1998<\/div>
Simulation Standard<\/div><\/div>

Cell Characterization with .MODIF Statement in SmartSpice<\/a><\/h3>
SmartSpice provides many unique and powerful features to facilitate parametric analysis in general and cell characterization in particular.<\/div><\/div><\/article>
January 1, 1998<\/div>
Simulation Standard<\/div><\/div>

Local Optimization Templates for Extracting BSIM3v3.1 Parameters in UTMOST III<\/a><\/h3>
The BSIM3v3.1 SPICE model has become an industry standard for modeling deep-submicron MOS technologies. The model is suitable for both digital and\u2026<\/div><\/div><\/article>
January 1, 1998<\/div>
Simulation Standard<\/div><\/div>

Hints, Tips, and Solutions – January 1998<\/a><\/h3>
Q: What is typical measurement set-up for the S3245A Noise Amplifier and what measurement equipment is used? A: Typical Measurement Set-Up<\/div><\/div><\/article><\/div>