{"id":34942,"date":"2021-01-26T11:28:27","date_gmt":"2021-01-26T19:28:27","guid":{"rendered":"https:\/\/silvaco.com\/single-dual-port-sram-compiler\/"},"modified":"2021-01-26T11:28:27","modified_gmt":"2021-01-26T19:28:27","slug":"single-dual-port-sram-compiler","status":"publish","type":"page","link":"https:\/\/silvaco.com\/zh-hans\/sipwareip\/foundation-ip\/embedded-memory-compilers\/single-dual-port-sram-compiler\/","title":{"rendered":"Single &#038; Dual Port SRAM Compilers"},"content":{"rendered":"<\/div><\/div><\/div><!-- close content main div --><\/div><\/div><div id='template_overview'  class='avia-section main_color avia-section-small avia-no-border-styling  avia-bg-style-scroll   container_wrap fullsize' style='background-color: #ffffff;  margin-top:0px; margin-bottom:0px; '  ><div class='container' ><div class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-34942'><div class='entry-content-wrapper clearfix'>\n<div class='flex_column_table av-equal-height-column-flextable -flextable' style='margin-top:20px; margin-bottom:0px; '><div class=\"flex_column av_three_fourth  flex_column_table_cell av-equal-height-column av-align-top first  \" style='padding:0px 0px 0px 0px ; border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/CreativeWork\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1>Single and Dual Port SRAM Compilers<\/h1>\n<div class=\"contentBlock\">\n<div class=\"line\">\n<div class=\"w100 txtjustify\">\n<h4><span style=\"font-size: 18px; font-weight: 600;\">Compilers Overview<\/span><\/h4>\n<p>Silvaco has 25 years&#8217; experience in compiled memory design. Its technology is silicon proven in thousands of designs and millions of wafers.<\/p>\n<ul>\n<li>Compilers for SRAM (single and dual Port), Register File (1 port and 2 port), and ROM<\/li>\n<li>Deployed at 12 different foundries and IDM\u2019s<\/li>\n<li>Available in processes down to 22nm<\/li>\n<\/ul>\n<h4>SRAM Compiler Features<\/h4>\n<ul>\n<li>Optimized for low power, general purpose and high performance applications<\/li>\n<li>Effective power management with multiple power modes and options<\/li>\n<li>High Performance through\u00a0Multiple voltage threshold (Vt) options and operating modes<\/li>\n<li>High Yield\n<ul>\n<li>Verified for global and local variation tolerant design<\/li>\n<li>ECC bits, word size and address flexibility for redundancy<\/li>\n<\/ul>\n<\/li>\n<li>Available technologies include 180nm, 152nm, 130nm, 110nm, 90nm, 85nm, 65nm, 55nm, 40nm, 28nm and 22nm<\/li>\n<li>CMOS processes variants covered include G, LP, SOI, and SRAMs in CMOS in the High Voltage, BCD, and eFlash foundry offerings<\/li>\n<li>Can easily port to other nodes and processes<\/li>\n<\/ul>\n<h4>SRAM Architecture<\/h4>\n<ul>\n<li>Designed primarily for low power operation<\/li>\n<li>High density option provides industry leading area and density<\/li>\n<li>Multiple low power modes for 55nm, 40nm and below include\u00a0Nap, Retention, Nap+Retention modes<\/li>\n<li>Embedded switches support<\/li>\n<li>Available in\n<ul>\n<li>Single supply<\/li>\n<li>Dual supply rail for periphery and core<\/li>\n<\/ul>\n<\/li>\n<li>Configurable write mask option<\/li>\n<li>Optional support for Built in Self Test and Repair (BIST\/R)<\/li>\n<\/ul>\n<\/div>\n<\/div>\n<\/div>\n<div class=\"contentBlock\">\n<div class=\"line\">\n<div class=\"w100 txtjustify\"><\/div>\n<\/div>\n<\/div>\n<\/div><\/section><br \/>\n<section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/CreativeWork\" ><div class='avia_textblock  '   itemprop=\"text\" ><table width=\"611\">\n<tbody>\n<tr>\n<td width=\"233\"><strong>Feature<\/strong><\/td>\n<td width=\"378\"><strong>Benefit<\/strong><\/td>\n<\/tr>\n<tr>\n<td width=\"233\">High density<\/td>\n<td width=\"378\">Industry leading area<\/td>\n<\/tr>\n<tr>\n<td width=\"233\">Partitioned array<\/td>\n<td width=\"378\">Extended battery life<\/td>\n<\/tr>\n<tr>\n<td width=\"233\">Several operating modes<\/td>\n<td width=\"378\">Up to 50% lower power consumption<\/td>\n<\/tr>\n<tr>\n<td width=\"233\">Data retention mode<\/td>\n<td width=\"378\">Reduce leakage current<\/td>\n<\/tr>\n<tr>\n<td width=\"233\">BIST (optional)<\/td>\n<td width=\"378\">Increase reliability and yield<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/div><\/section><br \/>\n<section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/CreativeWork\" ><div class='avia_textblock  '   itemprop=\"text\" ><h4>SRAM Low Power Operation Modes<\/h4>\n<p>Silvaco SRAM compilers offer a range of low power operation modes with different leakage and wake-up times.<\/p>\n<table width=\"539\">\n<tbody>\n<tr>\n<td width=\"138\"><strong>Mode<\/strong><\/td>\n<td width=\"325\"><strong>Description<\/strong><\/td>\n<td width=\"76\"><strong>Leakage*<\/strong><\/td>\n<\/tr>\n<tr>\n<td width=\"138\"><strong>Active<\/strong><\/p>\n<p>Core: On @ Vdd<br \/>\nPeriphery: On @ Vdd<\/td>\n<td width=\"325\">\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Read or write<\/p>\n<p>\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Core and Periphery powered and operational.<\/p>\n<p>\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Dynamic power and small Leakage power consumption<\/td>\n<td width=\"76\">&#8212;<\/td>\n<\/tr>\n<tr>\n<td width=\"138\"><strong>Standby<\/strong><\/p>\n<p>Core: On @ Vdd<br \/>\nPeriphery: On @ Vdd<\/td>\n<td width=\"325\">\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 No read or write.<\/p>\n<p>\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Core and Periphery powered but not operational<\/p>\n<p>\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Small Leakage power but no Dynamic power consumption<\/p>\n<p>\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Quick Wake Up time<\/td>\n<td width=\"76\"><strong>1.00 x<\/strong><\/td>\n<\/tr>\n<tr>\n<td width=\"138\"><strong>Nap*<\/strong><\/p>\n<p>Core: On @ Vdd<br \/>\nPeriphery: OFF<\/td>\n<td width=\"325\">\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Source Biasing turned on<\/p>\n<p><span style=\"font-family: inherit;\">\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Intermediate low power state<\/span><\/p>\n<p>\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Low leakage power consumption<\/p>\n<p>\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Quick Wake Up time (1 clock cycle), but a bit slower than Standby Wake Up time<\/td>\n<td width=\"76\"><strong>0.69 x<\/strong><\/td>\n<\/tr>\n<tr>\n<td width=\"138\"><strong>Retention*<\/strong><\/p>\n<p>Core: On @ &lt; Vdd<br \/>\nPeriphery: OFF<\/td>\n<td width=\"325\">\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Periphery power turned off<\/p>\n<p>\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Core at minimum voltage to retain data<\/p>\n<p>\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Lower Leakage power consumption than Nap<\/p>\n<p>\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Slow Wake Up time depends on powering up periphery switches and other circuits<\/td>\n<td width=\"76\"><strong>0.54 x<\/strong><\/td>\n<\/tr>\n<tr>\n<td width=\"138\"><strong>Retention + Nap*<\/strong><\/p>\n<p>Core: On @ Vdd<br \/>\nPeriphery: OFF<\/td>\n<td width=\"325\">\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Source Biasing turned on<\/p>\n<p>\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Core maintained at nominal voltage<\/p>\n<p>\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Lower Leakage power consumption than Retention<\/p>\n<p>\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Slow Wake up time depends on powering up periphery switches and other circuits<\/td>\n<td width=\"76\"><strong>0.28 x<\/strong><\/td>\n<\/tr>\n<tr>\n<td width=\"138\"><strong>Shutdown <\/strong>(Data Content Lost)<\/p>\n<p>Core: OFF<br \/>\nPeriphery: OFF<\/td>\n<td width=\"325\">\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Core and Periphery switched off<\/p>\n<p>\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Lowest Leakage power consumption<\/p>\n<p>\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Slowest Wake Up time<\/td>\n<td width=\"76\">&#8212;<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>*Advanced power modes are available for 55nm, 40nm, and below nodes.<\/p>\n<\/div><\/section><br \/>\n<section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/CreativeWork\" ><div class='avia_textblock  '   itemprop=\"text\" ><h4>Memory Configurations<\/h4>\n<p>Silvaco SRAM compilers support different voltage supply configurations.\u00a0 The compilers also support a wide range of mux and word width configurations.<\/p>\n<p data-wp-editing=\"1\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-16154 size-medium alignleft\" src=\"\/wp-content\/uploads\/2021\/01\/Single-Rail-SRAM-300x293.png\" alt=\"\" width=\"300\" height=\"293\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2021\/01\/Single-Rail-SRAM-300x293.png 300w, https:\/\/silvaco.com\/wp-content\/uploads\/2021\/01\/Single-Rail-SRAM-36x36.png 36w, https:\/\/silvaco.com\/wp-content\/uploads\/2021\/01\/Single-Rail-SRAM-38x37.png 38w, https:\/\/silvaco.com\/wp-content\/uploads\/2021\/01\/Single-Rail-SRAM-56x55.png 56w, https:\/\/silvaco.com\/wp-content\/uploads\/2021\/01\/Single-Rail-SRAM-48x48.png 48w, https:\/\/silvaco.com\/wp-content\/uploads\/2021\/01\/Single-Rail-SRAM.png 664w\" sizes=\"(max-width: 300px) 100vw, 300px\" \/> <img loading=\"lazy\" decoding=\"async\" class=\"alignleft wp-image-16153\" src=\"\/wp-content\/uploads\/2021\/01\/dual-supply-SRAM-300x278.png\" alt=\"\" width=\"316\" height=\"293\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2021\/01\/dual-supply-SRAM-300x278.png 300w, https:\/\/silvaco.com\/wp-content\/uploads\/2021\/01\/dual-supply-SRAM-40x37.png 40w, https:\/\/silvaco.com\/wp-content\/uploads\/2021\/01\/dual-supply-SRAM-59x55.png 59w, https:\/\/silvaco.com\/wp-content\/uploads\/2021\/01\/dual-supply-SRAM-48x45.png 48w, https:\/\/silvaco.com\/wp-content\/uploads\/2021\/01\/dual-supply-SRAM.png 700w\" sizes=\"(max-width: 316px) 100vw, 316px\" \/><\/p>\n<\/div><\/section><br \/>\n<section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/CreativeWork\" ><div class='avia_textblock  '   itemprop=\"text\" ><p><br class=\"avia-permanent-lb\" \/>Silvaco SRAM compilers also support embedded switches for finer integrated control of low power operation.<\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"alignleft wp-image-16152\" src=\"\/wp-content\/uploads\/2021\/01\/Single-Rail-SRAM-with-switches-300x300.png\" alt=\"\" width=\"300\" height=\"301\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2021\/01\/Single-Rail-SRAM-with-switches-300x300.png 300w, https:\/\/silvaco.com\/wp-content\/uploads\/2021\/01\/Single-Rail-SRAM-with-switches-80x80.png 80w, https:\/\/silvaco.com\/wp-content\/uploads\/2021\/01\/Single-Rail-SRAM-with-switches-36x36.png 36w, https:\/\/silvaco.com\/wp-content\/uploads\/2021\/01\/Single-Rail-SRAM-with-switches-180x180.png 180w, https:\/\/silvaco.com\/wp-content\/uploads\/2021\/01\/Single-Rail-SRAM-with-switches-37x37.png 37w, https:\/\/silvaco.com\/wp-content\/uploads\/2021\/01\/Single-Rail-SRAM-with-switches-55x55.png 55w, https:\/\/silvaco.com\/wp-content\/uploads\/2021\/01\/Single-Rail-SRAM-with-switches-48x48.png 48w, https:\/\/silvaco.com\/wp-content\/uploads\/2021\/01\/Single-Rail-SRAM-with-switches.png 664w\" sizes=\"(max-width: 300px) 100vw, 300px\" \/><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-16156 size-medium alignleft\" src=\"\/wp-content\/uploads\/2021\/01\/dual-supply-SRAM-with-switches2-300x300.png\" alt=\"\" width=\"300\" height=\"300\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2021\/01\/dual-supply-SRAM-with-switches2-300x300.png 300w, https:\/\/silvaco.com\/wp-content\/uploads\/2021\/01\/dual-supply-SRAM-with-switches2-80x80.png 80w, https:\/\/silvaco.com\/wp-content\/uploads\/2021\/01\/dual-supply-SRAM-with-switches2-36x36.png 36w, https:\/\/silvaco.com\/wp-content\/uploads\/2021\/01\/dual-supply-SRAM-with-switches2-180x180.png 180w, https:\/\/silvaco.com\/wp-content\/uploads\/2021\/01\/dual-supply-SRAM-with-switches2-37x37.png 37w, https:\/\/silvaco.com\/wp-content\/uploads\/2021\/01\/dual-supply-SRAM-with-switches2-55x55.png 55w, https:\/\/silvaco.com\/wp-content\/uploads\/2021\/01\/dual-supply-SRAM-with-switches2-48x48.png 48w, https:\/\/silvaco.com\/wp-content\/uploads\/2021\/01\/dual-supply-SRAM-with-switches2.png 663w\" sizes=\"(max-width: 300px) 100vw, 300px\" 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