How to Improve Physical Verification Productivity with SmartDRC/LVS
Physical Verification is the most critical stage of IC design. SmartDRC/LVS is a new physical verification tool for analog, digital and mixed-signal ICs including design rule checks (DRC), layout connectivity extraction and layout vs schematic (LVS) comparisons. Its unique multi-CPU architecture delivers high performance and capacity, accurate processing of complex shapes, and exceptional user productivity with fast interactive verification and intuitive debug. SmartDRC/LVS runsets are silicon-proven, and foundry certified.
SmartDRC/LVS is tightly integrated with Silvaco’s Expert layout editor and Gateway schematic editor. The integration enables users to visualize and pinpoint design issues and design rule violations and quickly act to resolve them. SmartLVS extracts the netlist from layout and provides the user the ability to cross-compare the schematic and layout.
What You Will Learn
- How SmartDRC/LVS improves productivity and accuracy of physical verification
- SmartRDE GUI Run and Debug environment for viewing progress and results
- Learn about SmartDRC/LVS PWRL (Power-L) rule language
- How the innovative One-Shot™ layout scanning technology delivers near-linear scaling and runtime predictability
Alex Grudanov is a Senior Director of Advanced R&D for Silvaco and was the former CEO and co-founder of POLYTEDA CLOUD LLC. Alex is a Cloud SaaS EDA pioneer and the first CEO of Ukrainian SME who won H2020 Phase2 grant funding from the European Commission.
WHO SHOULD ATTEND:
IP, Circuit, CAD, SoC and System design engineers, product managers and engineering management.
When: February 17, 2022