• 技术刊物 Simulation Standard

Simulation Standard

Silvaco面向半导体工艺和器件仿真工程师推出的技术刊物

Savage Enhanced with Recognition and Reporting of Hierarchical Structure of Errors

This article describes a method of reporting DRC errors implemented in Savage, applicable to multi-million transistor layouts. The method of hierarchical information inheritance is a perspective approach in an extension of capabilities of flat DRC systems. This technique makes it possible to report hierarchical errors in ordinary flat DRC systems.

Circuit Verification via Hypergraph Realization

One of the most challenging and time consuming tasks in VLSI design automation is Layout Versus Schematic (LVS). The problem is to test the consistency between the actual circuit, represented by the layout, and the nominal circuit upon which the design was based.

HINTS & TIPS – March 1998

Q: Is it possible to perform a DRC check on portions rather than on the whole circuit useful when only 2 or 3 errors to fix ?

3D Simulation of Power Devices Using Giga3D and MixedMode3D

Recent additions to the ATLAS device simulation framework have added the ability to simulate 3D electrothermal effects in Giga3D and mixed circuit simulation with 3D device simulation in MixedMode3D. The new modules add to the existing 3D device simulation within ATLAS as shown in Figure 1.

MixedMode Simulation of Power Electronic Converters

With mounting concern for energy conservation and nature preservation, power electronics is becoming increasingly dominant in everyday life.

Polysilicon Gate Depletion Effects in Sub-Micron MOSFETs

It is usually assumed that the poly gate in a MOSFET is doped at a concentration such that depletion in the gate either does not occur or that any depletion effects can safely be ignored. This article aims to quantify poly depletion effects for typical sub-micron device dimensions using ATHENA and ATLAS process and device simulators.