• 技术刊物 Simulation Standard

Simulation Standard

Silvaco面向半导体工艺和器件仿真工程师推出的技术刊物

Shallow-Trench-Isolation (STI) Effects in BSIM4 and HiSIM MOSFET Models in SmartSpice & UTMOST-III

There are several ways to account for the effect of STI-induced stress in standard compact models. The purpose of this article is to present two different approaches developed by the universities of Berkeley and Hiroshima. In both cases, new equations were derived and new parameters have been introduced in the latest versions of BSIM4 and HiSIM compact models. These new versions are currently supported by Silvaco SmartSpice/UTMOST softwares.

Behavioral Modeling of PLL Using Verilog-A with SmartSpice

In this article, we describe practical behavioral modeling for highly non-linear circuits using Verilog-A, which is analog extension of Verilog-AMS. At first, we describe behavioral modeling techniques for phase/frequency detectors (PFD) and voltage-controlled oscillators (VCO) those are essential part of phase-locked loop systems shown in Figure.1. Model parameter extraction techniques are described and demonstrated later. Finally, these models are simulated with SmartSpice and verified against the results of transistor circuit simulations.

Using Binned Device Models with SmartSpice

Q. My simulation fails because SmartSpice cannot find a binned model, what does this mean?

HIPEX-Net: Hierarchical Layout Extractor for Expert Editor

HIPEX-Net is a hierarchical layout extractor. It can create both hierarchical and flat SPICE formatted netlists of the extracted layout. HIPEX-Net also performs ERC (Electric Rule Checking) on the extracted netlist. This checks for connectivity errors in a chip design such as opens, shorts, and dangling nodes.

“Shortest Path” Option for Flight Line Style (Net Bar)

There is the recent improvement in Expert Layout Editor, the “Shortest path” option was added to Flight line styles (Net Bar). This option allows to build the shortest tree (network) connecting all selected nodes.

Expert Layout Editor Recent Improvements: Over-the-Point Drawing of Orthogonal Shapes

This article presents an overview of new features added to Silvaco's Expert layout editor. Silvaco has taken a careful look at the real-world obstacles faced daily by semiconductor layout designers and design engineers. Silvaco has augmented Expert with features that dramatically increase flexibility and also help to reduce constraint violations and other roadblocks inherent to complex layout design.