• 技术刊物 Simulation Standard

Simulation Standard

Silvaco面向半导体工艺和器件仿真工程师推出的技术刊物

Hints, Tips and Solutions – Crop and Slice using a non-convex mask in Victory Process export

Q. How can I Crop and Slice using a non-convex mask during the export?Non-Convex Mask Polygons Non-Convex Mask PolygonsPrevious Victory Process releases have supported convex polygon cropping, slicing and mirroring support. It is also now possible to use non-convex polygons for either cropping or slicing.In Figure 1 an example of a non-convex polygon crop and slice in the cell mode victory (delaunay) export is given. Note that the deck syntax is identical to the convex case.2D Crop, Slice and MirrorIt is possible to perform the crop, slice and mirror (process and/or device) in the 2D exports.An example of this functionality is given in Figure 3, where a crop and slice is shown. It should be noted that the coordinates specified in the polygon mask are those in the 2D export and not the 3D grid that the export is taken from (i.e., only X/Y need to be specified even though this cutplane is XZ).

Performance Evaluation of a New Hybrid MPI-thread Parallelized Direct Solver

The solution of linear systems lies in the core of any TCAD simulation. On any nonlinear step of the computation a linear system needs to be solved. The size and condition number of the matrices in these linear systems vary significantly depending on the specific type of TCAD simulation. So in order to achieve fast convergence it is required that the linear solver has good performance, good accuracy, can handle cases of ill-conditioned matrices, and it would be nice if the solver works well on any size linear system.

Deep Hole Etching Simulation for Advanced NAND Flash Memory

The NAND Flash memory cell has been refined to reduce the bit cost, but the limit of its miniaturization has been reached due to the high electric field problem and the difficulty of lithography. On that account, three-dimensional stack cell structures have been adopted to achieve mass storage devices [1-3]. It has already been reported that the fabrication of 256Gbit NAND Flash memory with 48 stacked layers started on August in 2015 [4, 5]. For the fabrication of the stack structures, it is necessary to realize etching of deep holes. For examples, if using 30nm design rules and one layer thickness is 40nm, its depth becomes 1.92um. If the holes diameter is 100 nm, its aspect ratio becomes 19.2. Then, in the next generation, the 512 Gbit flash memory cell will need the deep hole with the aspect ratio of 38.4 for 3.84um-depth. For investigating more suitable process conditions or optimum etched topography, accurate three-dimensional etching simulation is required, but it takes a very long time to simulate this deep hole etching accurately if using usual simulation methods like the Monte-Carlo method, because the aspect ratio of this deep hole is very large and therefore, the flux calculation effort of enhancing ions and neutral radical species is enourmous for a reactive enhanced ion etching (RIE) model.

Optical Simulation of Organic Light Emitting Diode by Transfer Matrix Method with a Green’s Function Approach and 2D FDTD

Organic light emitting diode (OLED) has been getting much attention over the past decades in the field of displays and lighting applications for its excellent efficiency, color quality and color tunability. Optical modeling of OLEDs is one important development issue to create high performance devices [1]. In this article, several optical simulations of OLEDs are presented by using recently implemented features in Atlas. First, we present the multiple dipole sources emission from a stacked layers structure, including the interference effect between the emitted light and reflected light using Transfer Matrix Method (TMM) with a Green’s Function Approach [2-4]. Then, we present the 2D FDTD analysis on the device with the grating structure using the finite difference time domain (FDTD) [5].

3D TCAD Mixed-Mode Simulation of Current Filaments in IGBT Multicell Array under Short-Circuit Condition

A power IGBT (Insulated Gate Bipolar Transistor) is conventionally made up of a repetitive array of homogenous IGBT cells. Such a homogenous configuration renders a uniform current flow across the active surface area of the IGBT chip when the IGBT is turned on. Under a short-circuit condition, however, the IGBT being turned on is exposed to a very high collector-to-emitter voltage. In this condition, the IGBT conducts a very high collector current, leading to correspondingly high power dissipation in the form of heat flowing uniformly across the chip. If the heating of the chip exceeds a critical level during a short-circuit operation, the device may fail or even get destroyed by local overheating in conjunction with the establishment of current filaments in a localized area, or the hot spots, within the device.

Hints, Tips and Solutions – Create scalable devices with Victory Process

Deckbuild supports variable substitution for both numerical and string variables using the SET statement and the $ symbol, thus allowing users to parameterize their input decks. The SET statement is used to generate a new variable and assign an initial value to it, e.g.,