• SiCure

SiCure IR, EM and Thermal Analysis

Silvaco’s SiCure®  performs IR-drop, EM and Thermal analysis on analog and mixed-signal IC designs.

Analysis of IR-drop and thermal effects have traditionally been a significant bottleneck in the physical verification of transistor level designs such as analog circuits, high-speed IOs, custom digital blocks, memories and standard cells. This is due to the need for accurate and increasingly complex analysis to be performed on designs that are progressively larger in size. For example, FinFET’s increased current density and thermal profile failure rate probabilities that must be managed with careful analysis and design.

SiCure overcomes these hurdles and accurately models IR-Drop and thermal effects for designs ranging from single block to full-chip.  SiCure utilizes a true built-in SPICE simulation engine, not simplified device models, for precision and applies parallel processing techniques to achieve performance. The result is physical measurement-like accuracy with high speed even on extremely large designs and applicability to all process nodes including FinFET technologies.

For a broad range of designs including processors, wired and wireless networks, sensors, high current ICs, and displays, Silvaco’s SiCure provides a user-friendly environment designed to assist quick turn-around-times and trouble free tape-outs.


  • Built-in SmartSpice engine
  • Comprehensive IR-drop analysis gives full visibility of supply networks from top-level connectors down to each transistor
  • Thermal analysis scales from single cell design to full chip and provides high accuracy of thermal analysis.
  • GDSII not required


  • Full chip sign-off with accurate and high performance analysis
  • Analysis available early in the back end design, when more design choices are available
  • Pre-characterization not required for analysis
  • Easy learning curve
  • Broad range of technology nodes supported


  • Analog and mixed-signal designs

Analog Custom Design Resources

Analog Simulation
Analog Custom Design & Analysis
Model Generation
Guardian DRC
Utmost IVGuardian LVS
Parasitic Extraction




Cameron Fisher
 MSC has found SmartSpice™ to be an excellent value in terms of easy integration, debug run time and total cost of simulation. Support during our learning curve has been great. MSC will be using SmartSpice™ for all future memory complier development.