• 1 & 2 Port Register File Compilers

1 and 2 Port Register File Memory Compilers

Compilers Overview

Silvaco has 25 years’ experience in compiled memory design. Its technology is silicon proven in thousands of designs and millions of wafers.

  • Compilers for SRAM (single and dual Port), Register File (1 port and 2 port), and ROM
  • Deployed at 12 different foundries and IDM’s
  • Available in processes down to 22nm

Register File Compiler Features

  • Optimized for low power, general purpose and high performance applications
  • Effective power management with multiple power modes and options
  • High Performance through Multiple voltage threshold (Vt) options and operating modes
  • High Yield
    • Verified for global and local variation tolerant design
    • ECC bits, word size and address flexibility for redundancy
  • Available technologies include 180nm, 152nm, 130nm, 110nm, 90nm, 85nm, 65nm, 55nm, 40nm, 28nm and 22nm
  • CMOS processes variants covered include G, LP, SOI, and SRAMs in CMOS in the High Voltage, BCD, and eFlash foundry offerings
  • Can easily port to other nodes and processes

Register File Memory Architecture

  • Proprietary architecture designed for high density and low power provides lower area
  • Multiple low power modes including Standby, Retention, and Shutdown modes
  • Embedded switches support
  • Available in
    • Single supply
    • Dual supply rail for periphery and core
  • Data retention mode
  • Byte mode for write operations
  • Optional support for Built in Self Test and Repair (BIST/R)
High densityIndustry leading area
Partitioned arrayExtended battery life
Several operating modesUp to 50% lower power consumption
Data retention modeReduce leakage current
BIST (optional)Increase reliability and yield

Register File Low Power Operation Modes

Silvaco Register File compilers offer a range of low power operation modes with different leakage and wake-up times.


Core: On @ Vdd
Periphery On @ Vdd

·       Read or write

·       Core and Periphery powered and operational.

·       Dynamic power and small Leakage power consumption


Core: On @ Vdd
Periphery On @ Vdd

·       No read or write.

·       Core and Periphery powered but not operational

·       Small Leakage power but no Dynamic power consumption

·       Quick Wake Up time

1.00 x

Core: On @ < Vdd
Periphery OFF

·       Periphery power turned off

·       Core at minimum voltage to retain data

·       Lower Leakage power consumption than Nap

·       Slow Wake Up time depends on powering up periphery switches and other circuits

0.54 x
Shutdown (Data Content Lost)

Core: OFF
Periphery OFF

·       Core and Periphery switched off

·       Lowest Leakage power consumption

·       Slowest Wake Up time

Memory Configurations

Silvaco Register File compilers support different voltage supply configurations.  The compilers also support a wide range of mux and word width configurations.