ATLAS/MixedMode Simulation of a Three Stage CMOS Ring Oscillator
Part I: MixedMode Setup
Ring oscillator circuits are a valuable test structure for determining the feasibility and success of an integrated circuit process fabrication sequence. One of the most useful results obtainable from a ring oscillator test structure is the delay time per gate. This information is especially important for successful design of high speed clock circuits, such as Phase Locked Loops (PLL’s) and Voltage Controlled Oscillators (VCO’s).
This article is aimed at demonstrating the simulation of a three stage CMOS ring oscillator. Using ATLAS/MixedMode, MOSFET devices in the circuit are simulated numerically. For Part I, both NMOS and PMOS devices were created with analytical doping profiles using ATLAS. In Part II these devices will be created from process simulation using ATHENA and process variations will be analyzed. Part II will be published in the next issue of the Simulation Standard.