• ROM Compiler

ROM Compiler

Compilers Overview

Silvaco has 25 years’ experience in compiled memory design. Its technology is silicon proven in thousands of designs and millions of wafers.

  • Compilers for SRAM (Single & Dual Port), Register File (1 port & 2 port), and ROM
  • Deployed at 12 different foundries and IDM’s
  • Available in processes down to 22nm

ROM Compiler Features

  • Unique bitcell and power architectures provides best combination of high density and low power
  • Compact VIA architecture
    • Ultra high density cells
    • High speed read times
    • Reduced stray capacitance
    • Reduced dynamic power consumption
  • Available technologies include 180nm, 152nm, 130nm, 110nm, 90nm, 85nm, 65nm, 55nm, 40nm, 28nm and 22nm
  • CMOS processes variants covered include G, LP, SOI, and SRAMs in CMOS in the High Voltage, BCD, and eFlash foundry offerings
  • Can easily port to other nodes and processes

ROM Architecture and Benefits

  • Via 1 programmable ROM with single programming layer for high density and reduced die cost
  • Extended Battery Life
    • Significant dynamic power reduction compared to alternative
    • Zero leakage in memory array
    • Minimal leakage in memory periphery
  • Easy integration
    • Large number of MUX options can be selected between 8 and 128
    • High flexibility for address range
  • High Yield design that is verified for global and local variation tolerance and mismatch