Simulate 40X Faster with SmartSpice HPP
In this webinar, we describe how SmartSpice HPP takes advantage of the modern multicore hardware platforms to speed up all internal aspects of transient simulations of analog circuits by adopting a partition-based simulation.
Using SmartSpice Compact Models
June 11, 2020 | 10:00 am – 10:30 am (PDT)
This webinar will provide a guide to developing Compact Models in SmartSpice to achieve optimal simulation performance. You will learn how models are used in SmartSpice and best practices when constructing a custom Verilog-A model.