Colin Shaw of Silvaco Named Si2 Pinnacle Award Winner

December 12, 2021

Improvement of Parasitic Capacitance Extraction Rules for Large-Scale Layout and Its Accuracy Verification Method

September 17, 2020 | 13:00 – 13:30 (JST) The accuracy of rule-based full-chip parasitic capacitance extraction tools including Silvaco's Hipex is highly dependent on the description of the rule files.

寄生参数缩减

Jivaro Pro：寄生参数缩减 加速您的SPICE仿真 Jivaro Pro是一款用于缩减寄生网表以减少仿真时间的独特解决方案。Jivaro Pro已被证明能够显著加快仿真进程，将仿真时间从数天减少到数小时。

Validation of CLEVER Interconnect Parasitics with 0.18 µm Process Measurements Benoit Froment and Herve Jaouen – SGS-Thomson Microelectronics

CLEVER can perform accurate field solver extractions of resistance and capacitance from 3D structures generated from realistic process simulation. Comparison of CLEVER results with measurements made by SGS-Thomson Microelectronics were done to validate the simulator.