Simulate 40X Faster with SmartSpice HPP
In this webinar, we describe how SmartSpice HPP takes advantage of the modern multicore hardware platforms to speed up all internal aspects of transient simulations of analog circuits by adopting a partition-based simulation.
Improvement of Parasitic Capacitance Extraction Rules for Large-Scale Layout and Its Accuracy Verification Method
September 17, 2020 | 13:00 – 13:30 (JST)
The accuracy of rule-based full-chip parasitic capacitance extraction tools including Silvaco's Hipex is highly dependent on the description of the rule files.
Model Extraction Flow with Utmost IV for Vertically Stacked Nanosheets Using the Leti-NSP Model
July 30, 2020 | 10:00 am – 10:30 am (PDT)
This webinar will provide a discussion of common methods used to secure an AMBA-based hardware and software system design.
Using SmartSpice Compact Models
June 11, 2020 | 10:00 am – 10:30 am (PDT)
This webinar will provide a guide to developing Compact Models in SmartSpice to achieve optimal simulation performance. You will learn how models are used in SmartSpice and best practices when constructing a custom Verilog-A model.
Machine Learning in the EDA-Specific Domain – 20 Years in the Making
June 25, 2020 | 10:00 am – 10:30 am (PDT)
This webinar will review these new approaches and how they are applied to different applications. Example ML-based EDA tools form Silvaco will be presented to illustrate what have been achieved.
TFT and OLED SPICE Modeling Using Utmost IV
May 14th 2020 | 10:00 am – 10:30 am (PDT)
In this webinar you will learn about SPICE modeling approaches and methods related to flat panel display applications using Silvaco’s Utmost IV modeling software. Topics covered include modeling of TFT devices, with emphasis on issues such as the frequency dispersion effect, and modeling of OLED devices, including the use of Verilog-A models and macromodels.
Utmost IV Quick-Start Model Optimization Templates
March 12th 2020 | 10:00 am - 11:00 am (PDT)
This webinar will present a new capability available in UTMOST IV: the Quick-Start Optimization Templates. This is a feature that allows users to quickly create an optimization project for a specific model, based on their data. It significantly increases the user’s productivity, at the same time requiring little or no prior SPICE modeling experience.
Circuit Rubberband
Real-time Circuit Simulation Rubberband Capability
With the rubberband feature of SmartSpice and Gateway analog design improvement is made easy. Changing values of models or device instance parameters in any combination provides realtime feedback on the change in circuit performance through the rubberband capability.