日志 Erick Castellon
What’s in the New MIPI Alliance I3C V1.1 Standard?
February 27th 2020 | 10:00 am – 11:00 am (PST)
I3C has the advantages in reducing pin count, increasing performance, and decreasing power while achieving some level of backwards compatibility with the long established I2C interface. The new I3C V1.1 announced in January 2020, enables faster interface speeds up to 100 Mhz and has many other new features that will aid the transition from I2C to I3C in applications.
Atomistic Analysis and Next Generation Computing at IEDM 2019
IEDM is THE device conference with more than a thousand participants from major companies and R&D institutes. Many talks were dedicated to new memory devices and circuits, including Ferroelectrics, MRAM, RRAM, driven by the requirements of AI processing. EUV is definitely there for 3nm and beyond. 3D integration was shown for LP-HP logic and RF. Gate-All-Around devices, with nanowires or nanosheets are mature versus FinFET.
TCAD Recommended Textbooks
CMOS: Mixed-Signal Circuit Design, Second Edition R. Ja […]
Customer Case Study: Using SmartSpice to Deliver Next-Generation, Low Power Memory Systems
At our SURGE Santa Clara event in October, Cameron Fisher, CEO of Mobile Semiconductor described their experience in adopting SmartSpice as their characterization engine for creating the database for their Trailblaze™ memory compiler software. Below is a summary of his talk.
Silvaco Exhibits and Presents Invited Paper on Atomistic Simulation at IEDM 2019
The IEEE International Electron Devices Meeting (IEDM) is the world’s preeminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. It is the flagship conference for
Nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices
Novel quantum and nano-scale devices and phenomenology
Optoelectronics, devices for power and energy harvesting, high-speed devices
Process technology and device modeling and simulation
Next Generation CMOS Nanowire: From Atoms to Circuit Simulation
Abstract— A complete simulation flow for a Nanowire-based ring oscillator circuit is presented, where the active devices were simulated using an atomistic device simulator. The results of this simulation have been fitted to an active device SPICE compact model, specifically formulated for nanowire/Gate all around Field Effect Transistors” (FETs). Finally, the active devices were incorporated into a SPICE netlist including back end resistance and capacitance parasitics.