日志 Erick Castellon

New Features in Expert Node Probing

6月 1, 2004在： /通过：

Expert’s Node Probing is powerful tool for inspection of netlist components on layout. It is designed for highlighting layout objects electrically connected with each others.

The additional features of Node Probing have been added in the new QT version of Expert. Because the layout extraction is being performed by hierarchical Guardian LPE, the user has possibility to get hierarchical node names troughout node tracing. The original net name in cell instance is keeping and is displaying aditionally to net name from top cell.

LPE Optimization with Clever/Hipex/Exact Linkage Methodology

5月 1, 2004在： /通过：

On the cutting edge of LSI design, the accuracy of Layout Parasitic Extraction (LPE) tools is a critical issue to miniaturized LSI design of rules measuring 0.13 um or lower. The quantitative consideration of coupling capacitance based on three-dimensional calculation is indispensable. Conventional advanced LSI design tools and methodology are limited in their ability to optimize the LPE library. As a result, the discussion of LPE tool accuracy and extracted parasitic results lack significant quantitative generality.

When solving for the static CV curve for a MOS capacitor, due to the absence of current carriers

5月 1, 2004在： /通过：

When solving for the static CV curve for a MOS capacitor, due to the absence of current carriers, convergence can be a real problem. Previous methods suggested in the hints and tips archive of Silvaco’s simulation standard have made use of Silvaco’s Luminous module where a small amount of light intensity is incident on the device, the idea being to generate a small amount of carriers to aid convergence.

IBIS Models Now Supported in SmartSpice

4月 1, 2004在： /通过：

Expert Parametric Wire (Pwire) is a complex group of objects containing, a single wire named master wire, any number of subparts such as enclosure wires, offset wires and sets of rectangles. Pwire objects enable extremely quick and efficient creation and editing of guard rings and shielded paths which are increasingly important due to higher integration density of IC designs.