Memory Statistical Characterization Solution with VarMan
With each new semiconductor process node, process variation, both global and local, play an increasingly significant role in determining Memory performance. When combined with supply voltage and temperature variation, traditional approaches to performing 6-sigma and over verification becomes impractical due to the large number of simulations that are required. Recently, 7-sigma verification with high precision and reasonable runtime became a real need! In this webinar we will review how the VarMan, from Silvaco, addresses these problems. The VarMan contains a suite of tools that includes Variability eXplorer, high-sigma Yield Estimation, high-sigma Performance Limit, and eXtreme Memory Analysis. These unique tools greatly reduce the number of simulations required for Memory characterization and quality assurance, while maintaining high accuracy, which makes design and characterization in the presence of variation feasible.
What attendees will learn:
- Key challenges of Memory Statistical Characterization
- Large number of process corners and multiple voltage points to explore
- Sensitivity significantly increase with new technology and advanced nodes & Situation complicated by local mismatch
- Huge number of simulations required for high-sigma verification
- Analyzing the whole Memory is still the ultimate need
- Confidence in High-Sigma results?
- Overview of statistics related to Memory statistical characterization
- Application of VarMan to Memory Characterization
- Variability eXplorer
- High-sigma performance limit and yield analysis
- eXtreme Memory Analysis
Dr. Jean Baptiste Duluc is the core-competency application engineer in charge of VarMan product development at Silvaco. He joined Silvaco in 1999 as support engineer for the characterization and modeling software Utmost. Then, at the research center, he leads projects in the new generation of characterization and modeling application, Utmost IV, and statistical model generation tool, Spayn. His PhD work was focused on process variation impacts on ﬁgure of merits of integrated circuits.
Dr. Duluc holds a MS and PhD in microelectronics from the University of Bordeaux, France.
When: September 20, 2018
Time: 10:00am-11:00am – (PST)
WHO SHOULD ATTEND:
Design and verification engineers and managers looking for solutions to increase the efficiency and accuracy of Memory statistical characterization.