Optimization of the Select Gate Transistor in a 3D NAND Memory Cell
This webinar will present the usage of TCAD process and device software for optimizing the operation of a 3D NAND memory cell with a focus on the select gate transistor. There are several design requirements specific to the select gate transistor in a 3D NAND memory cell. Low leakage current is needed to prevent memory read and program disturb errors that cause a shift in the threshold voltage of adjacent memory cells. Additionally, during memory read and erase operations, the gate transistor needs to provide enough current to drive the memory cells. In this webinar, we examine the design optimization of the select gate transistor with respect to various device elements including work function, source/drain overlap, and trap density. Finally, we cover reducing the channel length of the select gate transistor with respect to the use of dummy memory cells for threshold voltage control.
What attendees will learn:
- Challenges of 3D NAND scaling
- Requirements for a 3D NAND select gate transistor
- TCAD simulation of 3D NAND cell operations
- Read/program operation
- Erase operation
- Program disturb error
Dr. Jin Cho is Principal Application Engineer at Silvaco, based in Santa Clara, USA. Prior to joining Silvaco in 2018, he was with GLOBALFOUNDRIES/AMD for 15 years where he held the position of process/device manager of 14/10nm logic technology development and managed TCAD group for future device technology research. Jin holds a Ph. D. from Stanford University.
When: November 21, 2019
WHO SHOULD ATTEND:
Academics, engineers, and management looking for solutions to design and optimize 3D NAND cell operation.