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Next Generation of SoC Design: From Atoms to Systems

This webinar provides examples of how complex new technologies such as Flash memory, other advanced non-volatile memory technologies, and complex SoCs (such as Nvidia’s Xavier and Apple’s A12), use and re-use design IP at the architectural level, but require specialized new IPs that need to be simulated and analyzed down to the nanometer and atomic levels. The importance of simulation, emulation and design technology co-optimization (DTCO), along with fully verified and proven IPs for SoC design, is emphasized.

What attendees will learn:

  • Complex SoC, Flash Memory and Advanced Memory requirements and roadmaps
  • Using a solar panel example, show the use of simulation tools from the nanometer and atomic levels to the system module level
  • Design Technology Co-Optimization flow example using 2D and 3D TCAD simulations
  • Full SIPware design IP portfolio including cloud and enterprise IP management tools
    • Foundation IPs and customization tools for characterization
    • Automotive IPs
    • Controllers and PHYs for interconnect IP
    • IP Management including finger print and DNA analysis for accountability and security

Presenter

Dr. Babak Taheri, CTO and EVP of products at Silvaco. He is responsible for all aspects of the TCAD, EDA and IP product divisions.

Previously, he was the CEO and president of IBTechnologies working with investors, private equity firms, and startups on M&A, technology, and business diligence. While at IBTechnologies, he served on advisory boards of MEMS World Summit, Novasentis, AGCM, ALEA labs, Lion Point Capital, and Silver Lake. Prior to IBT, he was the VP & GM of the sensor solutions division at Freescale semiconductor (now NXP), VP & GM of Non-Volatile Memory product business unit at Cypress, and VP of Engineering at Invensense (now TDK).

Dr. Taheri holds a BS/MS in Electronics and a Ph.D. with majors in electrical engineering and neurosciences from UC Davis.

When: April 23, 2019
Where: Online
Time: 10:00am-11:00am-(PST)
Language: English

WHO SHOULD ATTEND:

Design Engineers, SoC designers, IP procurement, technology leaders and managers