Managing the Complexity of FinFET Standard Cell Layout with Cello
FinFET technologies have enabled designs with increased density and performance while reducing power, when compared to MOSFET. However, this comes at a cost of increased design complexity. Not only are some undesirable layout dependent effects more pronounced, but design rules have become much more complex. Many design rules violations can no longer be fixed within a local scope, since they may span a large region of a standard-cell and involve several polygons.
In this webinar we are going to review some of the most challenging aspects of FinFET standard-cell layout design, and how Silvaco’s Cello tool can be used to address these issues.
What You Will Learn
- FinFET overview and application
- FinFET layout design
- Using Cello for FinFET design and implementation
Presenter
Osvaldo Martinello is the Sr. R&D Director for the Foundation IP group at Silvaco, in Santa Clara, California, where he leads the development of tools for IP design and optimization. He holds a Computer Engineering degree and a Computer Science MSc, both received from UFRGS, in Porto Alegre, Brazil.
WHO SHOULD ATTEND:
IP, Circuit, CAD, SoC and System design engineers, product managers and engineering management.
When: February 10, 2022
Where: Online
Time: 10:00am-10:30am-(PST)
Language: English