Accurate Parasitic RC Extraction using Realistic 3D TCAD Structures
Accurate determination of RC parasitics is a key component in the design and integration of many state of the art semiconductor technologies. Often, the traditional flow of using rule based parasitic extraction can fall short due to accuracy limits, or isn’t possible because the LPE rule decks are not available. To address this issue, physics-based parasitic extraction utilizing field solvers are an optimal solution. Field-based solutions are optimal as extraction can occur on realistic 3D geometries, accurately taking into account the more detailed geometric effects influencing RC parastics.
What attendees will learn:
- Introduction to RC extraction – field solver vs rule-based approaches
- Silvaco flow solutions from TCAD to SPICE
- Silvaco Victory Process 3D TCAD – layout driven 3D structure prototyping or detailed physical TCAD process simulation Silvaco Clever – physics-based resistance and capacitance field solver Silvaco SmartSpice – Accurate SPICE simulation solution
- CMOS technologies including BEOL and MEOL parasitics
- Display design
- TCAD-to-Spice Flow
- 3D Structure generation, accurate RC extraction and SPICE circuit simulation to include MEOL parastics for FINFET-based circuits
Dr. Garrett Schlenvogt is a Senior Applications Engineer within the Silvaco TCAD division, based out of Silvaco’s east coast sales/support office in North Chelmsford, Massachusetts. He has been with Silvaco for 5 years, with responsibilities including presales and support of Silvaco TCAD customers for a wide variety of applications including: Advanced CMOS, Display Technologies, Sensors and Power/RF devices. Additionally, Garrett has lead multiple research proposals and collaborations for Silvaco, working with both with academic and commercial institutions. Prior to joining Silvaco, he was a research assistance at Arizona State University, with research focused on reliability simulation and modeling of CMOS technologies for harsh environments.
Dr. Schlenvogt holds a BSE, MS, and Ph.D in Electrical Engineering from Arizona State University in Tempe, Arizona
When: March 29, 2018
WHO SHOULD ATTEND:
Academics, engineers and management looking for solutions to circuit design and physical verification in ultra-thin chip, thin-film and hybrid flexible electronics.