• Hipex & Clever

Hipex and Clever Parasitic Extraction

Silvaco offers both rule and field-solver based RC parasitic extraction software.

Full-chip Rule-based RC Parasitic Extraction

Hipex-RC provides an accurate and fast solution for the extraction of parasitic capacitance and resistance from hierarchical layouts of analog, mixed-signal, memory IC and SoC designs. As part of Silvaco’s complete analog custom design flow, RC parasitic extraction together with DRC/LVs is tightly integrated with the Silvaco Expert layout editor.

Working from GDSII, cell netlists and rule-based technology files, Hipex-RC performs the parasitic extraction for either the full chip or selected nets or nodes, then back-annotates the schematic netlist with the exacted parasitics.

The device extraction capabilities of Hipex-RC allows the generation of hierarchical netlists that preserve the original layout hierarchy and supports a wide range of standard and parameterized user-defined devices. In addition it performs electrical rule checking (ERC) for shorts, opens and dangles.

Built for efficient parallelization on multi-processing servers, Hipex-RC is fast with efficient memory usage for large, full chip designs.

Field-Solver RC Parasitic Extraction

Silvaco has two field-solver RC parasitic extraction tools: Clever and Hipex-FS.

Hipex-FS is driven via the Silvaco Expert layout tool, for an designer-friendly 3D field solution based RC extraction, utilizing the same physics and solvers as Clever

Clever is a TCAD-like script based solution, and is ideal for detailed extraction of cell layouts and is a physics-based resistance and capacitance field solver for any arbitrary 3D shaped structure

Both Clever and Hipex-FS performs RC extraction with the highest accuracy, productivity and versatility for the most complicated interconnect cells, including realistic etching and deposition processes. The local adaptive-mesh refinement (AMR) feature allows the user to specify a desired accuracy. It will automatically refine the unstructured mesh where required, optimizing maximum accuracy, together with minimum simulation time.


  • Multiple options depending on size/complexity of design
  • Resolve complex non-planar geometries with structural accuracy for more precise RC extraction
  • User accuracy control for optimal runtime
  • Output in SPICE netlist form for universal compatibility


  • Advanced CMOS – FinFET, SOI, Bulk CMOS
  • Display – TFT, LCD, Touch Panel

TCAD Resources

TCAD of Innovative Nanodevices with Victory Atomistic



Accelerating Design with the Victory TCAD Suite

TCAD Simulations of RF-SOI Switches with Trap-Rich Substrate

For Next Generation Nanowires, Simulation from Atoms to SPICE


Accelerating Design with the Victory TCAD Suite

TCAD Simulations of RF-SOI Switches with Trap-Rich Substrate

For Next Generation Nanowires, Simulation from Atoms to SPICE


Coby Hanoch
 Silvaco provides state-of-the-art device models and TCAD tools that are widely used by semiconductor companies. We are excited to establish this joint development program with Silvaco so customers will have early access to our ReRAM technology on the most powerful simulation tools in the industry and can fast-track the release of their next-generation products. This is another key step by Weebit Nano to accelerate the incorporation of ReRAM technology by a larger number of OEM customers. 
Takashi Shinohe
 We are developing gallium oxide devices with a completely new proprietary manufacturing method. Utilizing a device simulator will become important in order to efficiently develop such new devices. For the decision to use Silvaco’s device simulator, the deciding factors were Silvaco’s extensive track record with wide band gap semiconductors, and Silvaco’s depth of knowledge of power devices. We expect to see even more progress in our development of GaO™ power devices as we move toward practical applications. 
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