Jivaro Runtime Reduction

Circuit Rubberband

Real-time Circuit Simulation Rubberband Capability With the rubberband feature of SmartSpice and Gateway analog design improvement is made easy. Changing values of models or device instance parameters in any combination provides realtime feedback on the change in circuit performance through the rubberband capability.

Customer Case Study: Using SmartSpice to Deliver Next-Generation, Low Power Memory Systems

At our SURGE Santa Clara event in October, Cameron Fisher, CEO of Mobile Semiconductor described their experience in adopting SmartSpice as their characterization engine for creating the database for their Trailblaze™ memory compiler software. Below is a summary of his talk.

SmartSpice Does It Smart

By this definition, any SPICE simulator qualifies as a smart design tool, but what about versatility? SmartSpice has had over 30 years of product development and is the Swiss Army knife of circuit simulators, with wide applicability to different CAD design flows.
Jivaro Runtime Reduction

On-Chip Variation and the Sign-off Timing Flow: An Industry Perspective

As semiconductor technology advances, the impact of on-chip variation increases, which means more sophisticated solutions are required.
Jivaro Runtime Reduction

Variation and Yield Analysis

Jivaro Runtime Reduction

Analog Simulation

Silvaco’s SmartSpice is a high performance parallel SPICE simulator that delivers industry leading accuracy. It is a proven, comprehensive solution for applications including simulation of complex high precision analog and mixed-signal circuits, memory, custom digital design and characterizing cell libraries of advanced semiconductor processes. It uses an intelligent architecture deploying multiple solvers, stepping algorithms and computation techniques. The result is accurate, robust convergence and industry leading performance and capacity – over 8 million active devices. It is compatible with HSPICE® and Spectre® for netlists, models, analysis features, and results – plus large libraries of calibrated device models are available. Featuring integration with Silvaco Gateway schematic editor and SmartView waveform viewer, SmartSpice fits seamlessly into front-end analog IC design flows.
Jivaro Runtime Reduction

Parasitic Reduction and Analysis

Jivaro is a unique stand-alone solution dedicated to the reduction of parasitic networks. It helps back-end verification teams speed up post-layout SPICE simulation of huge extracted parasitic circuits, while keeping high accuracy.Viso analyzes the electrical properties of RC parasitic networks which crucially impact circuit behavior in nanometer processes. These impacts affect circuit gain, delay, maximum clock rate, cross-coupling, level of ESD protection and other features, which can cripple a design. Viso’s parasitics-focused approach enables quick analysis of interconnect in order to pinpoint problems. It provides timing estimation and accurate comparison of different extracted netlists.Belledonne is used for layout comparison via extracted netlist. It compares two different extracted netlists and is mainly used for layout parasitic extraction (LPE) flow qualification.
Jivaro Runtime Reduction

SPICE Model Generation