Development of SPICE Model for CAAC-IGZO Multi-Gate FETs with Free Shape of Fin
May 31, 2022 | 13:00-13:30 (JST)
In this webinar, we will present a SPICE model of a crystalline oxide semiconductor CAAC-IGZO multi-gate FET developed jointly by Silvaco, Inc. and Semiconductor Energy Laboratory Co., Ltd. We have updated the model to cover a wider range of geometry parameters.
Learn How to Improve TFT-Based Flat Panel Designs with the Unique SmartSpice 4-Terminal TFT Model
April, 28, 2022 (PDT)
In this webinar, we will describe SmartSpice’s 4-terminal TFT compact model. Unique in the market, we present some of the characteristics of this compact model, and some of the degrees of freedom that it brings to both the modeling and the design teams.
Silvaco’s Dr. Firas Mohamed Elected to Co-chair of Si2 Artificial Intelligence/Machine Learning Special Interest Group
February 25, 2022
How to Optimize and Boost Your Device Modeling and Characterization with Utmost IV
March 10, 2022 | 10:00 am – 10:30 am (PST)
In this webinar we will examine some of the key features and advantages of Utmost IV for device modeling and characterization, and the major design flows where Utmost IV is a key component.
How to Improve Physical Verification Productivity with SmartDRC/LVS
February 17, 2022 | 10:00 am – 10:30 am (PST)
Physical Verification is the most critical stage of microchip design. This webinar introduces SmartDRC/LVS as a highly productive tool to perform physical verification of analog, digital and mixed-signal ICs.
Colin Shaw of Silvaco Named Si2 Pinnacle Award Winner
December 12, 2021
Silvaco SmartSpice 2021 – Top 10 New Features in the Baseline Release
August 19, 2021 | 10:00 am – 10:30 am (PDT)
In this webinar, we present the top 10 new features and improvements enabled by the SmartSpice team during this past year.
Achieve Your Display Design Performance Edge Through Precision Parasitic Extraction
June 29, 2021 | 10:00 am – 10:30 am (PDT)
In this webinar you will learn how Silvaco Hipex-FS can help designers find that edge in performance and innovation with the full force of realistic 3D process simulation.
Oxide Semiconductor LSI Technology and SPICE Model for Ultra Low Power LSI
May 12, 2021 | 13:00-13:40 (JST)
In this webinar, we will introduce CAAC-IGZOⓇ FET (c-axis aligned crystalline indium-gallium-zinc oxide FET) developed by Semiconductor Energy Laboratory Co., Ltd. (SEL) and the CAAC-IGZO FET SPICE model jointly developed by SEL and Silvaco.
How to Model and Simulate Flat Panel Pixel Arrays
May 13, 2021 | 10:00 am – 10:35 am (PDT)
In this webinar we will look at some of the effects to check when designing a flat panel.